Enhanced System Design and Scheduling Strategy for Switches in Time-Sensitive Networking. - Zhipeng Cao 001; Qinrang Liu; Dongpei Liu; Yanbin Hu (IEEE Access, 2021)

Modeling and Analysis of Waferscale Switching Network with Multiple System Faults. - Zhiquan Wan; Zhipeng Cao 001; Shunbin Li; Dehao Ye (ISCAS, 2024)

LBDR: A load-balanced deadlock-free routing strategy for chiplet systems. - Zhipeng Cao 001; Zhiquan Wan; Peijie Li; Qinrang Liu; Caining Wang; Yangxue Shao (Integr., 2024)

ETRS: efficient turn restrictions setting method for boundary routers in chiplet-based systems. - Zhipeng Cao 001; Wei Guo 018; Zhiquan Wan; Peijie Li; Qinrang Liu; Caining Wang; Yangxue Shao (J. Supercomput., 2024)

Enhancing interconnection network topology for chiplet-based systems: An automated design framework. - Zhipeng Cao 001; Qinrang Liu; Zhiquan Wan; Wenbo Zhang; Ke Song; Wenbin Liu (Future Gener. Comput. Syst., 2025)

A Multi-Objective Task Mapping Method for Enhancing Security Against Hardware Trojans in Heterogeneous Multi-Core System. - Bo Mei; Wenbo Zhang; Zhipeng Cao 001; Wei Guo 018; Mingquan Zhang; Wenbin Liu; Zheng Du (J. Circuits Syst. Comput., 2025)

MAHR: A Multi-Application Hybrid Reconfigurable Mechanism for Energy-Efficient Chiplet Interconnection Network. - Zhipeng Cao 001; Bo Mei; Qinrang Liu; Xue Pei; Zhiquan Wan; Caining Wang (J. Circuits Syst. Comput., 2025)

Architectural Exploration for Waferscale Switching System. - Zhiquan Wan; Zhipeng Cao 001; Shunbin Li; Peijie Li; Qingwen Deng; Weihao Wang; Kun Zhang; Guandong Liu; Ruyun Zhang; Qinrang Liu (IEEE Trans. Very Large Scale Integr. Syst., 2025)