Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths. - Zhiqiang You; Ken-ichi Yamaguchi; Michiko Inoue; Jacob Savir; Hideo Fujiwara (Asian Test Symposium, 2004)

Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths. - Zhiqiang You; Ken-ichi Yamaguchi; Michiko Inoue; Jacob Savir; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2005)

A Low Power Deterministic Test Using Scan Chain Disable Technique. - Zhiqiang You; Tsuyoshi Iwagaki; Michiko Inoue; Hideo Fujiwara (IEICE Trans. Inf. Syst., 2006)

DCScan: A Power-Aware Scan Testing Architecture. - Gui Dai; Zhiqiang You; Jishun Kuang; Jiedi Huang (ATS, 2008)

A Novel BIST Scheme Using Test Vectors Applied by Circuit-under-Test Itself. - Jishun Kuang; Ouyang Xiong; Zhiqiang You (ATS, 2008)

Test Response Data Volume and Wire Length Reductions for Extended Compatibilities Scan Tree Construction. - Yong-sheng Cheng; Zhiqiang You; Jishun Kuang (DELTA, 2008)

Capture in Turn Scan for Reduction of Test Data Volume, Test Application Time and Test Power. - Zhiqiang You; Jiedi Huang; Michiko Inoue; Jishun Kuang; Hideo Fujiwara (Asian Test Symposium, 2010)

Test Data Compression Using Four-Coded and Sparse Storage for Testing Embedded Core. - Ling Zhang; Jishun Kuang; Zhiqiang You (ICA3PP (2), 2010)

A GEO-Related IOT Applications Platform Based on Google Map. - Dayu Shi; Huaiyu Xu; Ruidan Su; Zhiqiang You (ICEBE, 2010)

Test Data Compression Using Selective Sparse Storage. - Ling Zhang; Jishun Kuang; Zhiqiang You (J. Electron. Test., 2011)

A scan disabling-based BAST scheme for test cost reduction. - Zhiqiang You; Weizheng Wang 002; Zhiping Dou; Peng Liu 045; Jishun Kuang (IEICE Electron. Express, 2011)

Test data compression using interval broadcast scan for embedded cores. - Ling Zhang; Jishun Kuang; Zhiqiang You (Microelectron. J., 2011)

Switching activity reduction for scan-based BIST using weighted scan input data. - Weizheng Wang 002; Jishun Kuang; Peng Liu 045; Xin Peng; Zhiqiang You (IEICE Electron. Express, 2012)

A scan disabling-based BAST scheme for test cost and test power reduction. - Zhiqiang You; Weizheng Wang 002; Peng Liu 045; Jishun Kuang; Zheng Qin (IEICE Electron. Express, 2012)

Thermal Simulation of Traction System for High-Speed Train Based on Heat Accumulation. - Huaiyu Xu; Jihui Xu; Zhiqiang You; Wenqi Peng; Kunlin Zhang; Jinfeng Xu (J. Comput., 2012)

Virtual scan chains reordering using a RAM-based module for high test compression. - Ling Zhang; Jishun Kuang; Zhiqiang You (Microelectron. J., 2012)

Achieving low capture and shift power in linear decompressor-based test compression environment. - Weizheng Wang; Jishun Kuang; Zhiqiang You (Microelectron. J., 2012)

Comparator and half adder design using complementary resistive switches crossbar. - Bosheng Liu; Zhiqiang You; Xiangrao Li; Jishun Kuang; Zheng Qin (IEICE Electron. Express, 2013)

A comprehensive metering scheme for intellectual property protection during both after-sale and evaluation periods of IC design. - Aobo Pan; Yaping Lin; Wenjie Che; Zhiqiang You; Yonghe Liu; Jinguo Li (IEICE Electron. Express, 2013)

Empirical studies on the network of social groups: the case of Tencent QQ. - Zhiqiang You; Xiao-Pu Han; Linyuan Lü; Chi Ho Yeung (CoRR, 2014)

An adaptive neural network A/D converter based on CMOS/memristor hybrid design. - Weiwei Wang; Zhiqiang You; Peng Liu; Jishun Kuang (IEICE Electron. Express, 2014)

Improve the compression ratios for code-based test vector compressions by decomposing. - Jishun Kuang; Liang Zhang; Zhiqiang You; Yingbo Zhou (ETS, 2015)

A signal degradation reduction method for memristor ratioed logic (MRL) gates. - Bosheng Liu; Ying Wang 001; Zhiqiang You; Yinhe Han 001; Xiaowei Li 001 (IEICE Electron. Express, 2015)

Logic operation-based DFT method and 1R memristive crossbar March-like test algorithm. - Peng Liu 045; Zhiqiang You; Jishun Kuang; Zhipeng Hu; Weizheng Wang 002 (IEICE Electron. Express, 2015)

An efficient small-delay faults simulator based on critical path tracing. - Tieqiao Liu; Jishun Kuang; Shuo Cai; Zhiqiang You (Int. J. Circuit Theory Appl., 2015)

A parallel-SSHI rectifier for ultra-low-voltage piezoelectric vibration energy harvesting. - Liao Wu; Jishun Kuang; Zhiqiang You; Peng Liu 045; Shuo Cai (IEICE Electron. Express, 2016)

Defect Analysis and Parallel March Test Algorithm for 3D Hybrid CMOS-Memristor Memory. - Peng Liu 045; Jigang Wu; Zhiqiang You; Michael Elimu; Weizheng Wang 002; Shuo Cai (ATS, 2018)

Optimistic value model of multidimensional uncertain optimal control with jump. - Liubao Deng; Zhiqiang You; Yuefen Chen (Eur. J. Control, 2018)

A novel memristor-based restricted Boltzmann machine for contrastive divergence. - Yan Chen; Zhiqiang You; Yingjie Zhang; Jishun Kuang; Jing Zhang (IEICE Electron. Express, 2018)

A Pseudo-Random Transform Decomposition Method for Improving the Coding Compression Ratio of Test Data. - Minghe Zhang; Jishun Kuang; Jing Huang; Zhiqiang You (HPCC/SmartCity/DSS, 2019)

Efficient data packet transmission algorithm for IPV6 mobile vehicle network based on fast switching model with time difference. - Wei Liang 005; Jing Long; Xia Lei; Zhiqiang You; Haibo Luo; Jiahong Cai; Kuan-Ching Li (Future Gener. Comput. Syst., 2019)

A high-performance CNN method for offline handwritten Chinese character recognition and visualization. - Pavlo Melnyk; Zhiqiang You; Keqin Li 001 (Soft Comput., 2020)

Fault Modeling and Efficient Testing of Memristor-Based Memory. - Peng Liu 045; Zhiqiang You; Jigang Wu; Bosheng Liu; Yinhe Han 001; Krishnendu Chakrabarty (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Integrating Two Logics Into One Crossbar Array for Logic Gate Design. - Lian Yao; Peng Liu 045; Jigang Wu; Yinhe Han 001; Yuehang Zhong; Zhiqiang You (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Defect Analysis and Parallel Testing for 3D Hybrid CMOS-Memristor Memory. - Peng Liu 045; Zhiqiang You; Jigang Wu; Michael Elimu; Weizheng Wang 002; Shuo Cai; Yinhe Han 001 (IEEE Trans. Emerg. Top. Comput., 2021)

DTTR: Detecting Text with Transformers. - Jing Yang; Zhiqiang You; Zhiwei Zhong; Peng Liu; Langqi Mei; Shenguang Huang (ICASSP, 2023)

A Complementary Resistive Switch-Based Balanced Ternary Logic. - Zhijian Peng; Peng Liu 045; Lian Yao; Zhiqiang You; Bosheng Liu; Yang Yi; Jigang Wu (ITC-Asia, 2024)

A Scan Slice Reordering Algorithm Based on Minimizing Entropy to Enhance Test Data Compression Efficiency. - Minghe Zhang; Guanglun Huang; Guoliang Ji; Zhiqiang You; Qiang Wu; Jianyu Cao (ITC-Asia, 2024)

A Dynamic Weight Quantization-Based Fault-tolerant Training Method for Ternary Memristive Neural Networks. - Zhiwei Zhong; Zhiqiang You; Peng Liu (ITC-Asia, 2024)

Fast and Lightweight Automatic Shipping Container Attributes Spotting. - Ruoxin Cheng; Zhiqiang You; Sovorn Chea; Gaode Wu; Kan Xia; Shenguang Huang (IEEE Trans. Instrum. Meas., 2025)