Optimization Space Exploration of Hardware Design for CRYSTALS-KYBER. - Yixuan Zhao; Zhiteng Chao; Jing Ye 001; Wen Wang 007; Yuan Cao 003; Shuai Chen; Xiaowei Li 001; Huawei Li 001 (ATS, 2020)

A Distributed ATPG System Combining Test Compaction Based on Pure MaxSAT. - Zhiteng Chao; Senlin Wang; Pengyu Tian; Shuwen Yuan; Huawei Li 001; Jing Ye 001; Xiaowei Li 001 (ATS, 2023)

A Fast Test Compaction Method for Commercial DFT Flow Using Dedicated Pure-MaxSAT Solver. - Zhiteng Chao; Xindi Zhang; Junying Huang; Jing Ye 001; Shaowei Cai 001; Huawei Li 001; Xiaowei Li 001 (ASPDAC, 2024)

A Static Test Compaction Method Based on GCN Assisted Fault Gate Classification. - Zhiteng Chao; Qinluan Dai; Jiale Li; Zizhen Liu; Wenxing Li; Hongqin Lyu; Jing Ye 001; Huawei Li 001; Xiaowei Li 001 (ITC-Asia, 2024)

HighTPI: A Hierarchical Graph Based Intelligent Method for Test Point Insertion. - Zhiteng Chao; Bin Sun; Hongqin Lyu; Ge Yu; Minjun Wang; Wenxing Li; Zizhen Liu; Jianan Mu; Shengwen Liang; Jing Ye 001; Xiaowei Li 001; Huawei Li 001 (VTS, 2025)

A fast test compaction method using dedicated Pure MaxSAT solver embedded in DFT flow. - Zhiteng Chao; Xindi Zhang; Junying Huang; Zizhen Liu; Yixuan Zhao; Jing Ye 001; Shaowei Cai 001; Huawei Li 001; Xiaowei Li 001 (Integr., 2025)

Extend IVerilog to Support Batch RTL Fault Simulation. - Jiaping Tang; Jianan Mu; Zizhen Liu; Zhiteng Chao; Jing Ye 001; Huawei Li 001 (CoRR, 2025)