Tunable Quasi-Circulator Based on a Compact Fully-Reconfigurable 180° Hybrid for Full-Duplex Transceivers. - Zhixian Deng; Huizhen Jenny Qian; Xun Luo (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 3.6dB NF, 23-39GHz Reflectionless RX with Absorptive Amplifier and Dual-Path Noise Cancelling LNA Supporting 64-QAM/256-QAM/1024-QAM for 5G NR. - Zhixian Deng; Huizhen Jenny Qian; Xun Luo (CICC, 2021)

A 22.9-38.2-GHz Dual-Path Noise-Canceling LNA With 2.65-4.62-dB NF in 28-nm CMOS. - Zhixian Deng; Jie Zhou 026; Huizhen Jenny Qian; Xun Luo (IEEE J. Solid State Circuits, 2021)

A 3.8-dB NF, 23-40GHz Phased-Array Receiver with 14-Bit Phase & Gain Manager and Calibration-Free Dual-Mode 28-52dB Image Rejection Ratio for 5G NR. - Zhixian Deng; Huizhen Jenny Qian; Changxuan Han; Yifan Li; Xun Luo (CICC, 2022)

A Reflectionless Receiver With Absorptive IF Amplifier and Dual-Path Noise-Canceling LNA. - Zhixian Deng; Huizhen Jenny Qian; Xun Luo (IEEE J. Solid State Circuits, 2022)

Compact SIDGS Filtering Power Divider With Three-Port 10-GHz Reflectionless Range. - Qingxian Li; Hongxin Tang; Deshan Tang; Zhixian Deng; Xun Luo (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

An 8-Element 23-40 GHz Continuously Auto Link-Tracking Phased-Array Transceiver with Time Division Modulator Achieving 7μs Tracking Time, 25.3% TX System Efficiency, 800MHz-64QAM Modulation for 5G NR. - Zhixian Deng; Bingzheng Yang; Wen Chen; Jie Zhou 026; Changxuan Han; Yifan Li; Yiyang Shu; Xun Luo (CICC, 2023)

A 4.8dB NF, 70-to-86GHz Deep-Noise-Canceling LNA Using Asymmetric Compensation Transformer and 4-to-1 Hybrid-Phase Combiner in 40nm CMOS. - Changxuan Han; Jie Zhou 026; Zhixian Deng; Yiyang Shu; Xun Luo (ISSCC, 2023)

A 28GHz Scalable Inter-Core-Shaping Multi-Core Oscillator with DM/CM-Configured Coupling Achieving 193.3dBc/Hz FoM and 205.5dBc/Hz FoMA at 1MHz Offset. - Yiyang Shu; Zhixian Deng; Xun Luo (ISSCC, 2023)

71-to-89GHz 12Gb/s Double-Edge-Triggered Quadrature RFDAC with LO Leakage Suppression Achieving 20.5dBm Peak Output Power and 20.4% System Efficiency. - Bingzheng Yang; Zhixian Deng; Huizhen Jenny Qian; Xun Luo (ISSCC, 2023)

A 23-40-GHz Phased-Array Receiver Using 14-Bit Phase-Gain Manager and Wideband Noise-Canceling LNA. - Zhixian Deng; Changxuan Han; Yifan Li; Huizhen Jenny Qian; Xun Luo (IEEE J. Solid State Circuits, 2023)

A 5.6-dB Noise Figure, 63-86-GHz Receiver Using a Wideband Noise-Cancelling Low Noise Amplifier With Phase and Amplitude Compensation. - Changxuan Han; Zhixian Deng; Yiyang Shu; Jun Yin 001; Pui-In Mak; Xun Luo (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A Phased-Array Transceiver With 2-Dimension Continuously Auto Link-Tracking Operation and Time Division Modulator. - Xun Luo; Bingzheng Yang; Zhixian Deng; Wen Chen; Yiyang Shu; Jie Zhou 026 (IEEE J. Solid State Circuits, 2024)