High parallel variation Banyan network based permutation network for reconfigurable LDPC decoder. - Xiao Peng 002; Zhixiang Chen 002; Xiongxin Zhao; Fumiaki Maehara; Satoshi Goto (ASAP, 2010)

An early stopping criterion for decoding LDPC codes in WiMAX and WiFi standards. - Zhixiang Chen 002; Xiongxin Zhao; Xiao Peng 002; Dajiang Zhou; Satoshi Goto (ISCAS, 2010)

Permutation Network for Reconfigurable LDPC Decoder Based on Banyan Network. - Xiao Peng 002; Zhixiang Chen 002; Xiongxin Zhao; Fumiaki Maehara; Satoshi Goto (IEICE Trans. Electron., 2010)

Generic Permutation Network for QC-LDPC Decoder. - Xiao Peng 002; Xiongxin Zhao; Zhixiang Chen 002; Fumiaki Maehara; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

A High Parallelism LDPC Decoder with an Early Stopping Criterion for WiMax and WiFi Application. - Zhixiang Chen 002; Xiongxin Zhao; Xiao Peng 002; Dajiang Zhou; Satoshi Goto (IPSJ Trans. Syst. LSI Des. Methodol., 2010)

A 115mW 1Gbps QC-LDPC decoder ASIC for WiMAX in 65nm CMOS. - Xiao Peng 002; Zhixiang Chen 002; Xiongxin Zhao; Dajiang Zhou; Satoshi Goto (A-SSCC, 2011)

A high parallel macro block level layered LDPC decoding architecture based on dedicated matrix reordering. - Qian Xie; Qian He; Xiao Peng 002; Ying Cui; Zhixiang Chen 002; Dajiang Zhou; Satoshi Goto (SiPS, 2011)

Ultra low power QC-LDPC decoder with high parallelism. - Ying Cui; Xiao Peng 002; Zhixiang Chen 002; Xiongxin Zhao; Yichao Lu; Dajiang Zhou; Satoshi Goto (SoCC, 2011)

A 6.72-Gb/s 8 pJ/bit/iteration IEEE 802.15.3c LDPC Decoder Chip. - Zhixiang Chen 002; Xiao Peng 002; Xiongxin Zhao; Leona Okamura; Dajiang Zhou; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

An efficient majority-logic based message-passing algorithm for non-binary LDPC decoding. - Yichao Lu; Nanfan Qiu; Zhixiang Chen 002; Satoshi Goto (APCCAS, 2012)

A 4320p 60fps H.264/AVC intra-frame encoder chip with 1.41Gbins/s CABAC. - Dajiang Zhou; Gang He 002; Wei Fei; Zhixiang Chen 002; Jinjia Zhou; Satoshi Goto (VLSIC, 2012)

A 115 mW 1 Gbps Bit-Serial Layered LDPC Decoder for WiMAX. - Xiongxin Zhao; Xiao Peng 002; Zhixiang Chen 002; Dajiang Zhou; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

DVB-T2 LDPC Decoder with Perfect Conflict Resolution. - Xiongxin Zhao; Zhixiang Chen 002; Xiao Peng 002; Dajiang Zhou; Satoshi Goto (IPSJ Trans. Syst. LSI Des. Methodol., 2012)

A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOS. - Zhixiang Chen 002; Xiao Peng 002; Xiongxin Zhao; Leona Okamura; Dajiang Zhou; Satoshi Goto (ASP-DAC, 2013)

A 24.5-53.6pJ/pixel 4320p 60fps H.264/AVC intra-frame video encoder chip in 65nm CMOS. - Dajiang Zhou; Gang He 002; Wei Fei; Zhixiang Chen 002; Jinjia Zhou; Satoshi Goto (ASP-DAC, 2013)

High-parallel performance-aware LDPC decoder IP core design for WiMAX. - Xiongxin Zhao; Zhixiang Chen 002; Xiao Peng 002; Dajiang Zhou; Satoshi Goto (MWSCAS, 2013)

A 5.83pJ/bit/iteration High-Parallel Performance-Aware LDPC Decoder IP Core Design for WiMAX in 65nm CMOS. - Xiongxin Zhao; Zhixiang Chen 002; Xiao Peng 002; Dajiang Zhou; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

High-Performance H.264/AVC Intra-Prediction Architecture for Ultra High Definition Video Applications. - Gang He 002; Dajiang Zhou; Wei Fei; Zhixiang Chen 002; Jinjia Zhou; Satoshi Goto (IEEE Trans. Very Large Scale Integr. Syst., 2014)

High-Throughput Power-Efficient VLSI Architecture of Fractional Motion Estimation for Ultra-HD HEVC Video Encoding. - Gang He 002; Dajiang Zhou; Yunsong Li; Zhixiang Chen 002; Tianruo Zhang; Satoshi Goto (IEEE Trans. Very Large Scale Integr. Syst., 2015)