LC-KO: A congestion-aware and area&timing-oriented placement method. - Zhixiong Di; Yanlong Wang; Shuang Qiao; Qianyin Xiang; Quanyuan Feng (ASICON, 2015)

A High-Throughput VLSI Architecture Design of Arithmetic Encoder in JPEG2000. - Zhixiong Di; Yue Hao 001; Jiangyi Shi; Peijun Ma (J. Signal Process. Syst., 2015)

A memory-based FFT processor using modified signal flow graph with novel conflict-free address schemes. - Yinghui Tian; Yong Hei; Zhizhe Liu; Zhixiong Di; Qi Shen 003; Zenghui Yu (IEICE Electron. Express, 2017)

Erratum: A memory-based FFT processor using modified signal flow graph with novel conflict-free address schemes [IEICE Electronics Express Vol. 14 (2017) No. 15 pp. 20170660]. - Yinghui Tian; Yong Hei; Zhizhe Liu; Zhixiong Di; Qi Shen 003; Zenghui Yu (IEICE Electron. Express, 2017)

High Parallel VLSI Architecture Design of BPC in JPEG2000. - Lintao Li; Jiangyi Shi; Zhixiong Di (ASICON, 2019)

A Modified Signal Flow Graph and Corresponding Conflict-Free Strategy for Memory-Based FFT Processor Design. - Yinghui Tian; Yong Hei; Zhizhe Liu; Qi Shen 003; Zhixiong Di; Tao Chen 007 (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A self-clocked binary-seaching digital low-dropout regulator with fast transient response. - Jiangyi Shi; Bo Zhao; Zhengguang Tang; Peijun Ma; Zhixiong Di (IEICE Electron. Express, 2020)

A local congestion elimination technique driven by overflow. - Wei Wu; Zhixiong Di; Jiangyi Shi; Quanyuan Feng; Zhengguang Tang (IEICE Electron. Express, 2020)

ASIC Design Principle Course with Combination of Online-MOOC and Offline-Inexpensive FPGA Board. - Zhixiong Di; Yongming Tang; Jiahua Lu; Zhaoyang Lv (ACM Great Lakes Symposium on VLSI, 2021)

A Power and Area Efficient Lepton Hardware Encoder with Hash-based Memory Optimization. - Xiao Yan 006; Zhixiong Di; Bowen Huang; Minjiang Li; Wenqiang Wang; Xiaoyang Zeng; Yibo Fan (CoRR, 2021)

Multi-electrostatic FPGA placement considering SLICEL-SLICEM heterogeneity and clock feasibility. - Jing Mai; Yibai Meng; Zhixiong Di; Yibo Lin (DAC, 2022)

Learned Compression Framework With Pyramidal Features and Quality Enhancement for SAR Images. - Zhixiong Di; Xuan Chen; Qiang Wu; Jiangyi Shi; Quanyuan Feng; Yibo Fan (IEEE Geosci. Remote. Sens. Lett., 2022)

Synthetic Aperture Radar Image Compression Based on a Variational Autoencoder. - Qihan Xu; Yunfan Xiang; Zhixiong Di; Yibo Fan; Quanyuan Feng; Qiang Wu; Jiangyi Shi (IEEE Geosci. Remote. Sens. Lett., 2022)

NBLG: A Robust Legalizer for Mixed-Cell-Height Modern Design. - Jinwei Chen; Zhixiong Di; Jiangyi Shi; Quanyuan Feng; Qiang Wu 014 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Detailed Routing Short Violation Prediction Using Graph-Based Deep Learning Model. - Xuan Chen; Zhixiong Di; Wei Wu; Qiang Wu; Jiangyi Shi; Quanyuan Feng (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A High-Throughput VLSI Architecture Design of Canonical Huffman Encoder. - Zhenyu Shao; Zhixiong Di; Quanyuan Feng; Qiang Wu; Yibo Fan; Xulin Yu; Wenqiang Wang (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Implementation of High Precision Error Amplification Scheme for AC-DC Converter. - Qiang Wu 014; Xun Li; Yongyuan Li; Zhixiong Di; Quanyuan Feng (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A High Throughput and Energy Efficient Lepton Hardware Encoder With Hash-Based Memory Optimization. - Xiao Yan 006; Zhixiong Di; Bowen Huang; Minjiang Li; Wenqiang Wang; Xiaoyang Zeng; Yibo Fan (IEEE Trans. Circuits Syst. Video Technol., 2022)

A Valley-Locking Control Scheme for an Audible Noise-Free Valley-Skip-Mode Flyback Converter. - Qiang Wu 014; Xun Li; Yueyun Han; Zhixiong Di; Quanyuan Feng (IEEE Trans. Ind. Electron., 2022)

OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit. - Jing Mai; Jiarui Wang; Zhixiong Di; Guojie Luo; Yun Liang 001; Yibo Lin (ASICON, 2023)

A Robust FPGA Router with Concurrent Intra-CLB Rerouting. - Jiarui Wang; Jing Mai; Zhixiong Di; Yibo Lin (ASP-DAC, 2023)

Multi-Electrostatic FPGA Placement Considering SLICEL-SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization. - Jing Mai; Jiarui Wang; Zhixiong Di; Yibo Lin (CoRR, 2023)

A unioned graph neural network based hardware Trojan node detection. - Weitao Pan; Meng Dong; Cong Wen; Hongjin Liu; Shaolin Zhang; Bo Shi; Zhixiong Di; Zhiliang Qiu; Yiming Gao 012; Ling Zheng (IEICE Electron. Express, 2023)

A High Precision CV Control Scheme for Low Power AC-DC BUCK Converter Controller. - Qiang Wu 014; Linjun Wu; Yongyuan Li; Xun Li; Zhixiong Di; Shubin Liu; Zhangming Zhu (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A Remote FPGA-based Experimental Teaching System Design Supporting Single-board Multi-user and Multi-board Single-user Operations in MOOCs. - Zhixiong Di; Xufeng Wei; Yiduo Chen; Shuanglong Wu; Peihao Sun; Qiang Wu 014 (ACM Great Lakes Symposium on VLSI, 2024)

Multielectrostatic FPGA Placement Considering SLICEL-SLICEM Heterogeneity, Clock Feasibility, and Timing Optimization. - Jing Mai; Jiarui Wang; Zhixiong Di; Yibo Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

LEAPS: Topological-Layout-Adaptable Multi-Die FPGA Placement for Super Long Line Minimization. - Zhixiong Di; Runzhe Tao; Jing Mai; Lin Chen; Yibo Lin (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Semi-Supervised Transfer Learning Framework for Aging-Aware Library Characterization. - Zhengguang Tang; Cong Li; Hailong You; Zhixiong Di; Linying Zhang; Xingming Liu; Yu Wang; Yong Dai; Geng Bai (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Imbalanced Large Graph Learning Framework for FPGA Logic Elements Packing Prediction. - Zhixiong Di; Runzhe Tao; Lin Chen; Qiang Wu; Yibo Lin (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

LEGALM: Efficient Legalization for Mixed-Cell-Height Circuits with Linearized Augmented Lagrangian Method. - Jing Mai; Chunyuan Zhao; Zuodong Zhang; Zhixiong Di; Yibo Lin; Runsheng Wang; Ru Huang 001 (ISPD, 2025)

A Robust FPGA Router With Optimization of High-Fanout Nets and Intra-CLB Connections. - Xun Jiang 002; Jiarui Wang; Jing Mai; Zhixiong Di; Yibo Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)