Refresh-aware loop scheduling for high performance low power volatile STT-RAM. - Keni Qiu; Junpeng Luo; Zhiyao Gong; Weigong Zhang; Jing Wang 055; Yuanchao Xu 002; Tao Li 006; Chun Jason Xue (ICCD, 2016)

Retention state-aware energy management for efficient nonvolatile processors: work-in-progress. - Keni Qiu; Zhiyao Gong; Dongqin Zhou; Weiwen Chen; Yongpan Liu (CODES+ISSS, 2017)

Retention state-enabled and progress-driven energy management for self-powered nonvolatile processors. - Zhiyao Gong; Keni Qiu; Dongqin Zhou; Weiwen Chen; Yuanchao Xu 002; Xin Shi; Yongpan Liu (RTCSA, 2017)

Pipeline Optimizations of Architecting STT-RAM as Registers in Rad-Hard Environment. - Zhiyao Gong; Keni Qiu; Weiwen Chen; Yuanhui Ni; Yuanchao Xu 002; Jianlei Yang 001 (TrustCom/BigDataSE/ICESS, 2017)

State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers. - Yuanhui Ni; Zhiyao Gong; Weiwen Chen; Chengmo Yang; Keni Qiu (VLSI Design, 2017)

Efficient energy management by exploiting retention state for self-powered nonvolatile processors. - Keni Qiu; Zhiyao Gong; Dongqin Zhou; Weiwen Chen; Yuanchao Xu 002; Xin Shi; Yongpan Liu (J. Syst. Archit., 2018)

Redesigning pipeline when architecting STT-RAM as registers in rad-hard environment. - Zhiyao Gong; Keni Qiu; Weiwen Chen; Yuanhui Ni; Yuanchao Xu 002; Jianlei Yang 001 (Sustain. Comput. Informatics Syst., 2019)