RouteNet: routability prediction for mixed-size designs using convolutional neural network. - Zhiyao Xie; Yu-Hung Huang; Guan-Qi Fang; Haoxing Ren; Shao-Yun Fang; Yiran Chen 001; Nvidia Corporation (ICCAD, 2018)

Routability-Driven Macro Placement with Embedded CNN-Based Prediction Model. - Yu-Hung Huang; Zhiyao Xie; Guan-Qi Fang; Tao-Chun Yu; Haoxing Ren; Shao-Yun Fang; Yiran Chen 001; Jiang Hu (DATE, 2019)

FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning. - Zhiyao Xie; Guan-Qi Fang; Yu-Hung Huang; Haoxing Ren; Yanqing Zhang 002; Brucek Khailany; Shao-Yun Fang; Jiang Hu; Yiran Chen 001; Erick Carvajal Barboza (ASP-DAC, 2020)

PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network. - Zhiyao Xie; Haoxing Ren; Brucek Khailany; Ye Sheng; Santosh Santosh; Jiang Hu; Yiran Chen 001 (ASP-DAC, 2020)

Routing-Free Crosstalk Prediction. - Rongjian Liang; Zhiyao Xie; Jinwook Jung; Vishnavi Chauha; Yiran Chen 001; Jiang Hu; Hua Xiang 001; Gi-Joon Nam (ICCAD, 2020)

Fast IR Drop Estimation with Machine Learning : Invited Paper. - Zhiyao Xie; Hai Li 001; Xiaoqing Xu; Jiang Hu; Yiran Chen 001 (ICCAD, 2020)

Fast IR Drop Estimation with Machine Learning. - Zhiyao Xie; Hai Li 001; Xiaoqing Xu; Jiang Hu; Yiran Chen 001 (CoRR, 2020)

Net2: A Graph Attention Network Method Customized for Pre-Placement Net Length Estimation. - Zhiyao Xie; Rongjian Liang; Xiaoqing Xu; Jiang Hu; Yixiao Duan; Yiran Chen 001 (ASP-DAC, 2021)

Automatic Routability Predictor Development Using Neural Architecture Search. - Chen-Chia Chang; Jingyu Pan; Tunhou Zhang; Zhiyao Xie; Jiang Hu; Weiyi Qi; Chung-Wei Lin; Rongjian Liang; Joydeep Mitra; Elias Fallon; Yiran Chen 001 (ICCAD, 2021)

APOLLO: An Automated Power Modeling Framework for Runtime Power Introspection in High-Volume Commercial Microprocessors. - Zhiyao Xie; Xiaoqing Xu; Matt Walker; Joshua Knebel; Kumaraguru Palaniswamy; Nicolas Hebert; Jiang Hu; Huanrui Yang; Yiran Chen 001; Shidhartha Das (MICRO, 2021)

Towards collaborative intelligence: routability estimation based on decentralized private data. - Jingyu Pan; Chen-Chia Chang; Zhiyao Xie; Ang Li 005; Minxue Tang; Tunhou Zhang; Jiang Hu; Yiran Chen 001 (DAC, 2022)

Robustify ML-Based Lithography Hotspot Detectors. - Jingyu Pan; Chen-Chia Chang; Zhiyao Xie; Jiang Hu; Yiran Chen 001 (ICCAD, 2022)

DEEP: Developing Extremely Efficient Runtime On-Chip Power Meters. - Zhiyao Xie; Shiyu Li 001; Mingyuan Ma; Chen-Chia Chang; Jingyu Pan; Yiran Chen 001; Jiang Hu (ICCAD, 2022)

The Dark Side: Security Concerns in Machine Learning for EDA. - Zhiyao Xie; Jingyu Pan; Chen-Chia Chang; Yiran Chen 001 (CoRR, 2022)

Intelligent Circuit Design and Implementation with Machine Learning. - Zhiyao Xie (CoRR, 2022)

Preplacement Net Length and Timing Estimation by Customized Graph Neural Network. - Zhiyao Xie; Rongjian Liang; Xiaoqing Xu; Jiang Hu; Chen-Chia Chang; Jingyu Pan; Yiran Chen 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Rethink before Releasing Your Model: ML Model Extraction Attack in EDA. - Chen-Chia Chang; Jingyu Pan; Zhiyao Xie; Jiang Hu; Yiran Chen 001 (ASP-DAC, 2023)

Fully Automated Machine Learning Model Development for Analog Placement Quality Prediction. - Chen-Chia Chang; Jingyu Pan; Zhiyao Xie; Yaguang Li; Yishuang Lin; Jiang Hu; Yiran Chen 001 (ASP-DAC, 2023)

PertNAS: Architectural Perturbations for Memory-Efficient Neural Architecture Search. - Afzal Ahmad; Zhiyao Xie; Wei Zhang 012 (DAC, 2023)

PROPHET: Predictive On-Chip Power Meter in Hardware Accelerator for DNN. - Jian Peng; Tingyuan Liang; Zhiyao Xie; Wei Zhang 012 (DAC, 2023)

Deep Subspace K-Means Clustering for Syringe Defect Detection Without Defective Samples. - Fei Yan; Xiaodong Wang; Longfu Hong; Zhiyao Xie (DSIE, 2023)

FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs. - Linfeng Du; Tingyuan Liang; Sharad Sinha; Zhiyao Xie; Wei Zhang 012 (FPGA, 2023)

A Noise Convolution Network for Tampering Detection. - Zhiyao Xie; Xiaochen Yuan; Chan-Tong Lam; Guoheng Huang (ICANN (10), 2023)

RA-Net: A Deep Learning Approach Based on Residual Structure and Attention Mechanism for Image Copy-Move Forgery Detection. - Kaiqi Zhao 004; Xiaochen Yuan; Zhiyao Xie; Guoheng Huang; Li Feng 001 (ICANN (10), 2023)

MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design. - Wenji Fang; Yao Lu; Shang Liu 006; Qijun Zhang; Ceyu Xu; Lisa Wu Wills; Hongce Zhang; Zhiyao Xie (ICCAD, 2023)

PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions. - Qijun Zhang; Shiyu Li 001; Guanglei Zhou; Jingyu Pan; Chen-Chia Chang; Yiran Chen 001; Zhiyao Xie (ICCAD, 2023)

Efficient Runtime Power Modeling with On-Chip Power Meters. - Zhiyao Xie (ISPD, 2023)

Security and Reliability Challenges in Machine Learning for EDA: Latest Advances. - Zhiyao Xie; Tao Zhang; Yifeng Peng (ISQED, 2023)

RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model. - Yao Lu; Shang Liu; Qijun Zhang; Zhiyao Xie (CoRR, 2023)

EDALearn: A Comprehensive RTL-to-Signoff EDA Benchmark for Democratized and Reproducible ML for EDA Research. - Jingyu Pan; Chen-Chia Chang; Zhiyao Xie; Yiran Chen 001 (CoRR, 2023)

RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution. - Shang Liu 006; Wenji Fang; Yao Lu; Qijun Zhang; Hongce Zhang; Zhiyao Xie (CoRR, 2023)

The Dark Side: Security and Reliability Concerns in Machine Learning for EDA. - Zhiyao Xie; Jingyu Pan; Chen-Chia Chang; Jiang Hu; Yiran Chen 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

SPA-Net: A Deep Learning Approach Enhanced Using a Span-Partial Structure and Attention Mechanism for Image Copy-Move Forgery Detection. - Kaiqi Zhao 004; Xiaochen Yuan; Zhiyao Xie; Yan Xiang; Guoheng Huang; Li Feng 001 (Sensors, 2023)

RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model. - Yao Lu; Shang Liu 006; Qijun Zhang; Zhiyao Xie (ASPDAC, 2024)

APPLE: An Explainer of ML Predictions on Circuit Layout at the Circuit-Element Level. - Tao Zhang; Haoyu Yang; Kang Liu; Zhiyao Xie (ASPDAC, 2024)

Accel-NASBench: Sustainable Benchmarking for Accelerator-Aware NAS. - Afzal Ahmad; Linfeng Du; Zhiyao Xie; Wei Zhang 012 (DAC, 2024)

Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization. - Wenji Fang; Shang Liu 006; Hongce Zhang; Zhiyao Xie (DAC, 2024)

OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation. - Shang Liu 006; Yao Lu; Wenji Fang; Mengming Li; Zhiyao Xie (ICCAD, 2024)

EDALearn: A Comprehensive RTL-to-Signoff EDA Benchmark for Democratized and Reproducible ML for EDA Research. - Jingyu Pan; Chen-Chia Chang; Zhiyao Xie; Yiran Chen 001; Hai Helen Li (ICCAD, 2024)

Unleashing Flexibility of ML-based Power Estimators Through Efficient Development Strategies. - Yao Lu; Qijun Zhang; Zhiyao Xie (ISLPED, 2024)

Large circuit models: opportunities and challenges. - Lei Chen; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Ru Huang 001; Yu Huang 005; Sadaf Khan; Min Li; Xingquan Li; Yu Li; Yun Liang 001; et al. (Sci. China Inf. Sci., 2024)

Erratum to: Large circuit models: opportunities and challenges. - Lei Chen; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Ru Huang 001; Yu Huang 005; Sadaf Khan; Min Li; Xingquan Li; Yu Li; Yun Liang 001; et al. (Sci. China Inf. Sci., 2024)

SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model. - Mengming Li; Wenji Fang; Qijun Zhang; Zhiyao Xie (CoRR, 2024)

AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs. - Wenji Fang; Mengming Li; Min Li 019; Zhiyuan Yan 003; Shang Liu 006; Hongce Zhang; Zhiyao Xie (CoRR, 2024)

The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models. - Lei Chen 002; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Yu Huang 005; Sadaf Khan; Min Li 019; Xingquan Li; Yun Liang 001; Yibo Lin; Jinwei Liu; et al. (CoRR, 2024)

ShortCircuit: AlphaZero-Driven Circuit Design. - Dimitrios Tsaras; Antoine Grosnit; Lei Chen 031; Zhiyao Xie; Haitham Bou-Ammar; Mingxuan Yuan (CoRR, 2024)

FirePower: Towards a Foundation with Generalizable Knowledge for Architecture-Level Power Modeling. - Qijun Zhang; Mengming Li; Yao lu; Zhiyao Xie (CoRR, 2024)

CAMU-Net: Copy-move forgery detection utilizing coordinate attention and multi-scale feature fusion-based up-sampling. - Kaiqi Zhao 004; Xiaochen Yuan; Tong Liu 021; Yan Xiang; Zhiyao Xie; Guoheng Huang; Li Feng 001 (Expert Syst. Appl., 2024)

Toward Fully Automated Machine Learning for Routability Estimator Development. - Chen-Chia Chang; Jingyu Pan; Zhiyao Xie; Tunhou Zhang; Jiang Hu; Yiran Chen 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs. - Linfeng Du; Tingyuan Liang; Xiaofeng Zhou; Jinming Ge; Shangkun Li; Sharad Sinha; Jieru Zhao; Zhiyao Xie; Wei Zhang 012 (ACM Trans. Reconfigurable Technol. Syst., 2024)

Data-Pattern-Based Predictive On-Chip Power Meter in DNN Accelerator. - Jian Peng; Tingyuan Liang; Jingbo Jiang; Yipu Zhang; Zhe Lin 007; Zhiyao Xie; Wei Zhang 012 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs. - Zhiyuan Yan 003; Wenji Fang; Mengming Li; Min Li 019; Shang Liu 006; Zhiyao Xie; Hongce Zhang (ASP-DAC, 2025)

PRICING: Privacy-Preserving Circuit Data Sharing Framework for Lithographic Hotspot Detection. - Chen-Chia Chang; Wan-Hsuan Lin; Jingyu Pan; Guanglei Zhou; Zhiyao Xie; Jiang Hu; Yiran Chen 001 (ASP-DAC, 2025)

A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks. - Wenji Fang; Shang Liu 006; Hongce Zhang; Zhiyao Xie (ASP-DAC, 2025)

Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage. - Shang Liu 006; Wenji Fang; Yao Lu; Qijun Zhang; Zhiyao Xie (ASP-DAC, 2025)

SMART-GPO: Gate-Level Sensitivity Measurement with Accurate Estimation for Glitch Power Optimization. - Yikang Ouyang; Yuchao Wu; Dongsheng Zuo; Subhendu Roy; Tinghuan Chen; Zhiyao Xie; Yuzhe Ma (ASP-DAC, 2025)

FirePower: Towards a Foundation with Generalizable Knowledge for Architecture-Level Power Modeling. - Qijun Zhang; Mengming Li; Yao Lu; Zhiyao Xie (ASP-DAC, 2025)

Pointer: An Energy-Efficient ReRAM-based Point Cloud Recognition Accelerator with Inter-layer and Intra-layer Optimizations. - Qijun Zhang; Zhiyao Xie (ASP-DAC, 2025)

Integrating Prefetcher Selection with Dynamic Request Allocation Improves Prefetching Efficiency. - Mengming Li; Qijun Zhang; Yongqing Ren; Zhiyao Xie (HPCA, 2025)

CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design. - Wenji Fang; Shang Liu; Jing Wang; Zhiyao Xie (ICLR, 2025)

Profile-Guided Temporal Prefetching. - Mengming Li; Qijun Zhang; Yichuan Gao; Wenji Fang; Yao Lu; Yongqing Ren; Zhiyao Xie (ISCA, 2025)

Transferable Presynthesis PPA Estimation for RTL Designs With Data Augmentation Techniques. - Wenji Fang; Yao Lu; Shang Liu 006; Qijun Zhang; Ceyu Xu; Lisa Wu Wills; Hongce Zhang; Zhiyao Xie (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

A Two-Phase Scheme by Integration of Deep and Corner Feature for Balanced Copy-Move Forgery Localization. - Tong Liu 021; Xiaochen Yuan; Zhiyao Xie; Kaiqi Zhao 004; Guoheng Huang; Chi-Man Pun (IEEE Trans. Ind. Informatics, 2025)

OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation. - Shang Liu; Yao Lu; Wenji Fang; Mengming Li; Zhiyao Xie (CoRR, 2025)

A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA. - Wenji Fang; Jing Wang; Yao Lu; Shang Liu; Yuchao Wu; Yuzhe Ma; Zhiyao Xie (CoRR, 2025)

NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph. - Wenji Fang; Wenkai Li; Shang Liu 006; Yao Lu; Hongce Zhang; Zhiyao Xie (CoRR, 2025)

GenEDA: Unleashing Generative Reasoning on Netlist via Multimodal Encoder-Decoder Aligned Foundation Model. - Wenji Fang; Jing Wang; Yao Lu; Shang Liu; Zhiyao Xie (CoRR, 2025)

RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique. - Shang Liu 006; Wenji Fang; Yao Lu; Jing Wang 171; Qijun Zhang; Hongce Zhang; Zhiyao Xie (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

LithoExp: Explainable Two-stage CNN-based Lithographic Hotspot Detection with Layout Defect Localization. - Cong Jiang; Haoyang Sun; Dan Feng 001; Zhiyao Xie; Benjamin Tan 001; Kang Liu 017 (ACM Trans. Design Autom. Electr. Syst., 2025)

HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutions. - Jing Wang; Shang Liu; Yao Lu; Zhiyao Xie (CoRR, 2025)

An Architecture-Level CPU Modeling Framework for Power and Other Design Qualities. - Qijun Zhang; Mengming Li; Andrea Mondelli; Zhiyao Xie (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring. - Dimitris Tsaras; Xing Li; Lei Chen; Zhiyao Xie; Mingxuan Yuan (CoRR, 2025)

AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group Decoupling. - Qijun Zhang; Yao Lu; Mengming Li; Zhiyao Xie (CoRR, 2025)

ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis. - Wenkai Li; Yao Lu; Wenji Fang; Jing Wang; Qijun Zhang; Zhiyao Xie (CoRR, 2025)

Image Manipulation Localization Using Dual-Shallow Feature Pyramid Fusion and Boundary Contextual Incoherence Enhancement. - Yan Xiang; Xiaochen Yuan; Kaiqi Zhao 004; Tong Liu 021; Zhiyao Xie; Guoheng Huang; Jianqing Li 001 (IEEE Trans. Emerg. Top. Comput. Intell., 2025)

A noise-assistant network for tampering detection via inconspicuous feature enhancement and multi-perspective perception. - Zhiyao Xie; Xiaochen Yuan; Chan-Tong Lam; Guoheng Huang; Nuno Lourenço 002 (Expert Syst. Appl., 2026)