Optical measurement system for characterizing compound semiconductor interface and surface states. - Matthias Passlack; Ronald N. Legge; Diana Convey; Zhiyi Yu; Jonathan K. Abrokwah (IEEE Trans. Instrum. Meas., 1998)

Hardware and applications of AsAP: An asynchronous array of simple processors. - Bevan M. Baas; Zhiyi Yu; Michael J. Meeuwsen; Omar Sattari; Ryan W. Apperson; Eric W. Work; Jeremy W. Webb; Michael A. Lai; Daniel Gurman; Chi Chen; Jason Cheung; Dean Truong; et al. (Hot Chips Symposium, 2006)

Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles. - Zhiyi Yu; Bevan M. Baas (ICCD, 2006)

An asynchronous array of simple processors for dsp applications. - Zhiyi Yu; Michael J. Meeuwsen; Ryan W. Apperson; Omar Sattari; Michael A. Lai; Jeremy W. Webb; Eric W. Work; Tinoosh Mohsenin; Mandeep Singh; Bevan M. Baas (ISSCC, 2006)

Performance and Power Analysis of Globally Asynchronous Locally Synchronous Multi-Processor Systems. - Zhiyi Yu; Bevan M. Baas (ISVLSI, 2006)

A Shared Memory Module for Asynchronous Arrays of Processors. - Michael J. Meeuwsen; Zhiyi Yu; Bevan M. Baas (EURASIP J. Embed. Syst., 2007)

AsAP: A Fine-Grained Many-Core Platform for DSP Applications. - Bevan M. Baas; Zhiyi Yu; Michael J. Meeuwsen; Omar Sattari; Ryan W. Apperson; Eric W. Work; Jeremy W. Webb; Michael A. Lai; Tinoosh Mohsenin; Dean Truong; Jason Cheung (IEEE Micro, 2007)

A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains. - Ryan W. Apperson; Zhiyi Yu; Michael J. Meeuwsen; Tinoosh Mohsenin; Bevan M. Baas (IEEE Trans. Very Large Scale Integr. Syst., 2007)

A low-area interconnect architecture for chip multiprocessors. - Zhiyi Yu; Bevan M. Baas (ISCAS, 2008)

AsAP: An Asynchronous Array of Simple Processors. - Zhiyi Yu; Michael J. Meeuwsen; Ryan W. Apperson; Omar Sattari; Michael A. Lai; Jeremy W. Webb; Eric W. Work; Dean Truong; Tinoosh Mohsenin; Bevan M. Baas (IEEE J. Solid State Circuits, 2008)

Architecture and Evaluation of an Asynchronous Array of Simple Processors. - Zhiyi Yu; Michael J. Meeuwsen; Ryan W. Apperson; Omar Sattari; Michael A. Lai; Jeremy W. Webb; Eric W. Work; Tinoosh Mohsenin; Bevan M. Baas (J. Signal Process. Syst., 2008)

A 167-Processor Computational Platform in 65 nm CMOS. - Dean Nguyen Truong; Wayne H. Cheng; Tinoosh Mohsenin; Zhiyi Yu; Anthony T. Jacobson; Gouri Landge; Michael J. Meeuwsen; Christine Watnik; Anh Thien Tran; Zhibin Xiao; Eric W. Work; Jeremy W. Webb; et al. (IEEE J. Solid State Circuits, 2009)

High Performance, Energy Efficiency, and Scalability With GALS Chip Multiprocessors. - Zhiyi Yu; Bevan M. Baas (IEEE Trans. Very Large Scale Integr. Syst., 2009)

A scalable and fault-tolerant routing algorithm for NoCs. - Zewen Shi; Kaidi You; Yan Ying; Bei Huang; Xiaoyang Zeng; Zhiyi Yu (ISCAS, 2010)

A Cost-Efficient LDPC Decoder for DVB-S2 with the Solution to Address Conflict Issue. - Yan Ying; Dan Bao; Zhiyi Yu; Xiaoyang Zeng; Yun Chen 001 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

A Low-Area Multi-Link Interconnect Architecture for GALS Chip Multiprocessors. - Zhiyi Yu; Bevan M. Baas (IEEE Trans. Very Large Scale Integr. Syst., 2010)

A control scheme for a 65nm 32×32b 4-read 2-write register file. - Jun Han 003; Xingxing Zhang; Baoyu Xiong; Zhiyi Yu; Xiaoyang Zeng (ASICON, 2011)

A channel estimator for LTE downlink mapped on a multi-core processor platform. - Maofei He; Jiajie Zhang; Wenhua Fan; Zhiyi Yu; Xiaoyang Zeng (ASICON, 2011)

A method of quadratic programming for mapping on NoC architecture. - Jiayi Sheng; Liulin Zhong; Ming-e Jing; Zhiyi Yu; Xiaoyang Zeng (ASICON, 2011)

Design of a single-ended cell based 65nm 32×32b 4R2W register file. - Baoyu Xiong; Xingxing Zhang; Jun Han 003; Zhiyi Yu; Xiaoyang Zeng (ASICON, 2011)

Modified Minimal-Connected-Component fault block model to deal with defective links and nodes for 2D-mesh NoCs. - Yueming Yang; Heng Quan; Zewen Shi; Xiaoyang Zeng; Zhiyi Yu (ASICON, 2011)

A low power 1.0 GHz VCO in 65nm-CMOS LP-process. - Zhang Zhang 004; Zhiyi Yu; Xu Cheng 002; Xiaoyang Zeng (ASICON, 2011)

An optimized mapping algorithm based on Simulated Annealing for regular NoC architecture. - Liulin Zhong; Jiayi Sheng; Ming-e Jing; Zhiyi Yu; Xiaoyang Zeng; Dian Zhou (ASICON, 2011)

A reconfigurable and deadlock-free routing algorithm for 2D Mesh Network-on-Chip. - Zewen Shi; Yueming Yang; Xiaoyang Zeng; Zhiyi Yu (ISCAS, 2011)

Fault tolerant computing for stream DSP applications using GALS multi-core processors. - Zhiyi Yu; Zewen Shi; Xiaoyang Zeng (ISCAS, 2011)

A Scalable and Reconfigurable Fault-Tolerant Distributed Routing Algorithm for NoCs. - Zewen Shi; Xiaoyang Zeng; Zhiyi Yu (IEICE Trans. Inf. Syst., 2011)

Evaluating performance of manycore processors with various granularities considering yield and lifetime reliability. - Yueming Yang; Zewen Shi; Jianming Yu; Liulin Zhong; Xiaoyang Zeng; Zhiyi Yu (ISCAS, 2012)

A pure software ldpc decoder on a multi-core processor platform with reduced inter-processor communication cost. - Yan Ying; Kaidi You; Liyang Zhou; Heng Quan; Ming-e Jing; Zhiyi Yu; Xiaoyang Zeng (ISCAS, 2012)

Task-binding based branch-and-bound algorithm for NoC mapping. - Liyang Zhou; Ming-e Jing; Liulin Zhong; Zhiyi Yu; Xiaoyang Zeng (ISCAS, 2012)

A low-cost architecture for multi-mode Reed-Solomon decoder. - Yun Chen 001; Yuebin Huang; Wei Meng; Zhiyi Yu; Xiaoyang Zeng (ISOCC, 2012)

An 800MHz 320mW 16-core processor with message-passing and shared-memory inter-core communication mechanisms. - Zhiyi Yu; Kaidi You; Ruijin Xiao; Heng Quan; Peng Ou; Yan Ying; Haofan Yang 001; Ming-e Jing; Xiaoyang Zeng (ISSCC, 2012)

A 64×32bit 4-read 2-write low power and area efficient register file in 65nm CMOS. - Jun Han 003; Xingxing Zhang; Yi Li; Baoyu Xiong; Yuejun Zhang; Zhang Zhang 004; Zhiyi Yu; Xu Cheng 002; Xiaoyang Zeng (IEICE Electron. Express, 2012)

Design of a high information-density multiple valued 2-read 1-write register file. - Yuejun Zhang; Pengjun Wang; Baoyu Xiong; Zhiyi Yu (IEICE Electron. Express, 2012)

Efficient Implementation of OFDM Inner Receiver on a Programmable Multi-Core Processor Platform. - Wenhua Fan; Chen Chen 011; Yun Chen 001; Zhiyi Yu; Xiaoyang Zeng (IEICE Trans. Commun., 2012)

A Fully Programmable Reed-Solomon Decoder on a Multi-Core Processor Platform. - Bei Huang; Kaidi You; Yun Chen 001; Zhiyi Yu; Xiaoyang Zeng (IEICE Trans. Inf. Syst., 2012)

A hybrid router combining circuit switching and packet switching with virtual channels for on-chip networks. - Jie Lin; Wei Zhou; Zhiyi Yu; Xiaoyang Zeng (ASICON, 2013)

A fast multi-core virtual platform and its application on software development. - Zongyan Wang; Dexue Zhang; Xueqiu Yu; Zhiyi Yu; Xiaoyang Zeng (ASICON, 2013)

Efficient implementation of 3780-point FFT on a 16-core processor. - Haofan Yang 001; Kedong Chen; Shengqiong Xie; Ming-e Jing; Zhiyi Yu; Xiaoyang Zeng (ASICON, 2013)

A turbo decoder implementation for LTE downlink mapped on a multi-core processor platform. - Qing Zhang; Xueqiu Yu; Zhiyi Yu; Xiaoyang Zeng (ASICON, 2013)

A 2D mesh NoC with self-configurable and shared-FIFOs routers. - Wei Zhou; Jianming Yu; Jie Lin; Zhiyi Yu; Xiaoyang Zeng (ASICON, 2013)

H.264 video parallel decoder on a 24-core processor. - Shikai Zhu; Zheng Yu 001; Shile Cui; Zhiyi Yu; Xiaoyang Zeng (ASICON, 2013)

Implementation and optimization of 3780-point FFT on multi-core system. - Ming-e Jing; Zhiyi Yu; Xiaoyang Zeng; Jiayi Sheng; Haofan Yang 001 (ISCAS, 2013)

Time-Division-Multiplexer based routing algorithm for NoC system. - Ming-e Jing; Zhiyi Yu; Xiaoyang Zeng; Liyang Zhou (ISCAS, 2013)

A low power register file with asynchronously controlled read-isolation and software-directed write-discarding. - Zheng Yu 001; Jiajie Zhang; Xueqiu Yu; Xiaoyang Zeng; Zhiyi Yu (ISCAS, 2013)

A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array. - Peng Ou; Jiajie Zhang; Heng Quan; Yi Li; Maofei He; Zheng Yu 001; Xueqiu Yu; Shile Cui; Jie Feng; Shikai Zhu; Jie Lin; Ming-e Jing; et al. (ISSCC, 2013)

Efficient distributed memory management in a multi-core H.264 decoder on FPGA. - Jiajie Zhang; Zheng Yu 001; Zhiyi Yu; Kexin Zhang; Zhonghai Lu; Axel Jantsch (ISSoC, 2013)

Architecture and Physical Implementation of Reconfigurable Multi-Port Physical Unclonable Functions in 65 nm CMOS. - Pengjun Wang; Yuejun Zhang; Jun Han 003; Zhiyi Yu; Yibo Fan; Zhang Zhang 004 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Parallelization of Radix-2 Montgomery Multiplication on Multicore Platform. - Jun Han 003; Shuai Wang; Wei Huang; Zhiyi Yu; Xiaoyang Zeng (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Acceleration of Naive-Bayes algorithm on multicore processor for massive text classification. - Lijun Zhou; Zhiyi Yu; Jie Lin; Shikai Zhu; Weijing Shi; Haijie Zhou; Kunpeng Song; Xiaoyang Zeng (ISIC, 2014)

An area-efficient dual replica-bitline delay technique for process-variation-tolerant low voltage SRAM sense amplifier timing. - Yi Li; Liang Wen; Yuejun Zhang; Xu Cheng 002; Jun Han 003; Zhiyi Yu; Xiaoyang Zeng (IEICE Electron. Express, 2014)

A 16-Core Processor With Shared-Memory and Message-Passing Communications. - Zhiyi Yu; Ruijin Xiao; Kaidi You; Heng Quan; Peng Ou; Zheng Yu 001; Maofei He; Jiajie Zhang; Yan Ying; Haofan Yang 001; Jun Han 003; Xu Cheng 002; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Low-Power Multicore Processor Design With Reconfigurable Same-Instruction Multiple Process. - Zheng Yu 001; Zhiyi Yu; Xueqiu Yu; Ningxi Liu; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

An Efficient Implementation of Montgomery Multiplication on Multicore Platform With Optimized Algorithm, Task Partitioning, and Network Architecture. - Renfeng Dou; Jun Han 003; Yifan Bo; Zhiyi Yu; Xiaoyang Zeng (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A lifting-based 2-D discrete wavelet transform architecture for data compression of bio-potential signals. - Yi Ren; Jun Han 003; Zhiyi Yu; Sizhong Xuan; Xiaoyang Zeng (ASICON, 2015)

Parallel implementation of AES on 2.5D multicore platform with hardware and software co-design. - Jielin Wang; Weizhen Wang; Jianwei Yang; Zhiyi Yu; Jun Han 003; Xiaoyang Zeng (ASICON, 2015)

A configurable SoC design for information security. - Sizhong Xuan; Jun Han 003; Zhiyi Yu; Yi Ren; Xiaoyang Zeng (ASICON, 2015)

A scalable and reconfigurable 2.5D integrated multicore processor on silicon interposer. - Jie Lin; Shikai Zhu; Zhiyi Yu; Dongjun Xu; Sai Manoj P. D.; Hao Yu 001 (CICC, 2015)

Non-binary digital calibration for split-capacitor DAC in SAR ADC. - Yawei Guo; Yue Wu; Dongdong Guo; Xu Cheng 002; Zhiyi Yu; Xiaoyang Zeng (IEICE Electron. Express, 2015)

Special Issue on Emerging Many-Core Systems for Exascale Computing. - Masoud Daneshtalab; Farhad Mehdipour; Zhiyi Yu; Hannu Tenhunen (ACM J. Emerg. Technol. Comput. Syst., 2015)

A Heterogeneous Multicore Crypto-Processor With Flexible Long-Word-Length Computation. - Jun Han 003; Renfeng Dou; Lingyun Zeng; Shuai Wang; Zhiyi Yu; Xiaoyang Zeng (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A 65 nm Cryptographic Processor for High Speed Pairing Computation. - Jun Han 003; Yang Li; Zhiyi Yu; Xiaoyang Zeng (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Many-Core Processors Granularity Evaluation by Considering Performance, Yield, and Lifetime Reliability. - Jianming Yu; Wei Zhou; Yueming Yang; Xiaodong Zhang 024; Zhiyi Yu (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Design and Analysis of Highly Energy/Area-Efficient Multiported Register Files With Read Word-Line Sharing Strategy in 65-nm CMOS Process. - Xiaoyang Zeng; Yi Li; Yuejun Zhang; Shujie Tan; Jun Han 003; Xingxing Zhang; Zhang Zhang 004; Xu Cheng 002; Zhiyi Yu (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A fast and energy efficient FPGA-based system for real-time object tracking. - Xiaobai Chen; Jinlong Xu; Zhiyi Yu (APSIPA, 2017)

The write deduplication mechanism based on a novel low-power data latched sense amplifier for a magnetic tunnel junction based non-volatile memory. - Baofa Huang; Ningyuan Yin; Zhiyi Yu (ASICON, 2017)

Parallel implementations of SHA-3 on a 24-core processor with software and hardware co-design. - Jianwei Yang; Weizhen Wang; Zhicheng Xie; Jun Han 003; Zhiyi Yu; Xiaoyang Zeng (ASICON, 2017)

A multi-core-based heterogeneous parallel turbo decoder. - Jianmin Zeng; Chubin Wu; Zhang Zhang 004; Xin Cheng 001; Guangjun Xie; Jun Han 003; Xiaoyang Zeng; Zhiyi Yu (IEICE Electron. Express, 2017)

A Scalable Network-on-Chip Microprocessor With 2.5D Integrated Memory and Accelerator. - Sai Manoj P. D.; Jie Lin; Shikai Zhu; Yingying Yin; Xu Liu 002; Xiwei Huang; Chongshen Song; Wenqi Zhang; Mei Yan; Zhiyi Yu; Hao Yu 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

An FPGA-Based Hardware Accelerator for Traffic Sign Detection. - Weijing Shi; Xin Li 001; Zhiyi Yu; Gary Overett (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A Reconfigurable Process Engine for Flexible Convolutional Neural Network Acceleration. - Xiaobai Chen; Shanlin Xiao; Zhiyi Yu (APSIPA, 2018)

An Automatic Task Partition Method for Multi-core System. - Ming-e Jing; Yujie Huang; Yibo Fan; Xiaoyong Xue; Xiaoyang Zeng; Zhiyi Yu (ISCAS, 2018)

A Flexible and Energy-Efficient Convolutional Neural Network Acceleration With Dedicated ISA and Accelerator. - Xiaobai Chen; Zhiyi Yu (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A 68-mw 2.2 Tops/w Low Bit Width and Multiplierless DCNN Object Detection Processor for Visually Impaired People. - Xiaobai Chen; Jinglong Xu; Zhiyi Yu (IEEE Trans. Circuits Syst. Video Technol., 2019)

SPA: Stochastic Probability Adjustment for System Balance of Unsupervised SNNs. - Xingyu Yang; Mingyuan Meng; Shanlin Xiao; Zhiyi Yu (ICPR, 2020)

An Asynchronous Convolution Process Engine forVGG-16 Neural Network. - Junshu Lin; Weikun Liu; Xusheng Li; Shanlin Xiao; Zhiyi Yu (ICTA, 2020)

A Low-Power Processing Element Based on Asynchronous Data-Driven Bit-Serial Multiplier for CNNs. - Weikun Liu; Junshu Lin; Xusheng Li; Shanlin Xiao; Zhiyi Yu (ICTA, 2020)

Spiking Inception Module for Multi-layer Unsupervised Spiking Neural Networks. - Mingyuan Meng; Xingyu Yang; Shanlin Xiao; Zhiyi Yu (IJCNN, 2020)

A Low-Cost and High-Throughput NoC-Aware Chip-to-Chip Interconnection. - Wenkang Liao; Yuhao Guo; Shanlin Xiao; Zhiyi Yu (ISCAS, 2020)

BioSNet: A Fast-Learning and High-Robustness Unsupervised Biomimetic Spiking Neural Network. - Mingyuan Meng; Xingyu Yang; Shanlin Xiao; Zhiyi Yu (CoRR, 2020)

DM-IMCA: A dual-mode in-memory computing architecture for general purpose processing. - Jianmin Zeng; Zhang Zhang 004; Runhao Chen; Shiyue Liang; Tianlin Cao; Zhiyi Yu; Xin Cheng 001; Guangjun Xie (IEICE Electron. Express, 2020)

Low-Cost Adaptive Exponential Integrate-and-Fire Neuron Using Stochastic Computing. - Shanlin Xiao; Wei Liu 118; Yuhao Guo; Zhiyi Yu (IEEE Trans. Biomed. Circuits Syst., 2020)

NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators. - Shanlin Xiao; Yuhao Guo; Wenkang Liao; Huipeng Deng; Yi Luo; Huanliang Zheng; Jian Wang 080; Cheng Li; Gezi Li; Zhiyi Yu (IEEE Trans. Very Large Scale Integr. Syst., 2020)

3D-VNPU: A Flexible Accelerator for 2D/3D CNNs on FPGA. - Huipeng Deng; Jian Wang 080; Huafeng Ye; Shanlin Xiao; Xiangyu Meng 003; Zhiyi Yu (FCCM, 2021)

FWUA : A Flexible Winograd-Based Uniform Accelerator for 1D/2D/3D CNNs. - Jian Wang 080; Huipeng Deng; Huafeng Ye; Shanlin Xiao; Zhiyi Yu (ICTA, 2021)

A high throughput spatially coupled low density generator matrix coding system. - Ziyuan Luo; Qingyi Xie; Shanlin Xiao; Zhiyi Yu (ICTA, 2021)

High-Throughput Zipper Encoder for 800G Optical Communication System. - Qingyi Xie; Ziyuan Luo; Shanlin Xiao; Kai Wang; Zhiyi Yu (ICTA, 2021)

OERFF: A Vehicle Re-Identification Method Based on Orientation Estimation and Regional Feature Fusion. - Bin Zheng; Zhengbao Lei; Chen Tang; Jin Wang 001; Zhuofan Liao; Zhiyi Yu; Yiming Xie (IEEE Access, 2021)

Dimension fusion: Dimension-level dynamically composable accelerator for convolutional neural networks. - Huipeng Deng; Jian Wang 080; Huafeng Ye; Shanlin Xiao; Xiangyu Meng 003; Zhiyi Yu (IEICE Electron. Express, 2021)

High-parallelism Inception-like Spiking Neural Networks for Unsupervised Feature Learning. - Mingyuan Meng; Xingyu Yang; Lei Bi 001; Jinman Kim; Shanlin Xiao; Zhiyi Yu (Neurocomputing, 2021)

Hand gesture recognition algorithm combining hand-type adaptive algorithm and effective-area ratio for efficient edge computing. - Qiang Zhang 034; Shanlin Xiao; Zhiyi Yu; Huanliang Zheng; Peng Wang (J. Electronic Imaging, 2021)

A Data-Driven Asynchronous Neural Network Accelerator. - Shanlin Xiao; Weikun Liu; Junshu Lin; Zhiyi Yu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

An MTJ-Based Asynchronous System With Extremely Fine-Grained Voltage Scaling. - Ningyuan Yin; Baofa Huang; Xiaobai Chen; Jianjun Chen; Zhiyi Yu (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A Low-Power Asynchronous RISC-V Processor With Propagated Timing Constraints Method. - Zhiyu Li; Yuhao Huang; Longfeng Tian; Ruimin Zhu; Shanlin Xiao; Zhiyi Yu (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Balancing the Cost and Performance Trade-Offs in SNN Processors. - Huanliang Zheng; Yuhao Guo; Xingyu Yang; Shanlin Xiao; Zhiyi Yu (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

One Case of THOUGHT: Industry-University Converged Education Practice on Open Source. - Zhiyi Yu; Chao Li; Chaochen Hu; Zhen Chen; Yandong Yao; Jiang Wu; Hao Wang; Jialun Du; Min Guo; Haoyu Wang; Weimin Li; Xiu Li; et al. (ICCSE (3), 2022)

3D-NWA: A Nested-Winograd Accelerator for 3D CNNs. - Huafeng Ye; Huipeng Deng; Jian Wang 080; Mingyu Wang 003; Zhiyi Yu (ICTA, 2022)

DFT Architecture for Click-Based Bundled-Data Asynchronous Circuits. - Ruimin Zhu; Zeyang Xu; Yuhao Huang; Shanlin Xiao; Zhiyi Yu (ICTA, 2022)

Hardware Based RISC-V Instruction Set Randomization. - Sheng Zuo; Junjie Zhuang; Yao Liu; Mingyu Wang; Zhiyi Yu (ICTA, 2022)

An in-memory computing multiply-and-accumulate circuit based on ternary STT-MRAMs for convolutional neural networks. - Guihua Zhao; Xing Jin 005; Huafeng Ye; Yating Peng; Wei Liu; Ningyuan Yin; Weichong Chen; Jianjun Chen; Ximing Li 003; Zhiyi Yu (IEICE Electron. Express, 2022)

A dual-rail/single-rail hybrid system using null convention logic circuits. - Wenzha Yang; Yong Ma; Jiajie Yan; Yang Chen; Shanlin Xiao; Zhiyi Yu (Microelectron. J., 2022)

An Asynchronous Bundled-Data Template With Current Sensing Completion Detection Technique. - Yuhao Huang; Shanlin Xiao; Zhiyu Li; Zhiyi Yu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

CRAFT: Common Router Architecture for Throughput Optimization. - Jiahua Yan; Mingyu Wang; Yao Qin; Zhiyi Yu (ICA3PP (3), 2023)

LWSDP: Locality-Aware Warp Scheduling and Dynamic Data Prefetching Co-design in the Per-SM Private Cache of GPGPUs. - Wangguang Wang; Mingyu Wang 003; Yicong Zhang; Yukun Wei; Zhiyi Yu (ICPADS, 2023)

A Scalable Deadlock-Free Static Routing Algorithm for Chiplet-Based Systems. - Xiaoran Zhang; Mingyu Wang 003; Yicong Zhang; Tao Lu; Zhiyi Yu (ICPADS, 2023)

Towards Efficient On-Chip Learning for Spiking Neural Networks Accelerator with Surrogate Gradient. - Kexin Huang; Wei Liu; Yue Liu; Shanlin Xiao; Zhiyi Yu (ICTA, 2023)

Towards Energy-Efficient Asynchronous Circuit Design with Flip-Flop-to-Latch Replacement. - Zeyang Xu; Shanlin Xiao; Lingfeng Zhou; Bohan Wang; Zhiyi Yu (ICTA, 2023)

A 1.97 TFLOPS/W Configurable SRAM-Based Floating-Point Computation-in-Memory Macro for Energy-Efficient AI Chips. - Yangzhan Mai; Mingyu Wang 003; Chuanghao Zhang; Baiqing Zhong; Zhiyi Yu (ISCAS, 2023)

A Digital SRAM Computing-in-Memory Design Utilizing Activation Unstructured Sparsity for High-Efficient DNN Inference. - Baiqing Zhong; Mingyu Wang 003; Chuanghao Zhang; Yangzhan Mai; Xiaojie Li; Zhiyi Yu (ISVLSI, 2023)

Enabling energy-Efficient object detection with surrogate gradient descent in spiking neural networks. - Jilong Luo; Shanlin Xiao; Yinsheng Chen; Zhiyi Yu (CoRR, 2023)

A 6T-3M SOT-MRAM for in-memory computing with reconfigurable arithmetic operations. - Xing Jin 005; Ningyuan Yin; Weichong Chen; Ximing Li 003; Guihua Zhao; Zhiyi Yu (IEICE Electron. Express, 2023)

A Low Insertion Loss Wideband Bonding-Wire Based Interconnection for 400 Gbps PAM4 Transceivers. - Xiangyu Meng; Yecong Li; Zhiyi Yu (IEICE Trans. Electron., 2023)

A Low Power 100-Gb/s PAM-4 Driver with Linear Distortion Compensation in 65-nm CMOS. - Xiangyu Meng; Kangfeng Wei; Zhiyi Yu; Xinlun Cai (IEICE Trans. Electron., 2023)

Computing Resistance-Style Image Sensors for Artificial Neural Networks. - Guihua Zhao; Yating Peng; Yizhan Wang; Caihua Wan; Xianping Liu; Yu Zhang; Xiufeng Han; Weichong Chen; Zhiyi Yu (IEEE Internet Things J., 2023)

Re-Cache: Mitigating cache contention by exploiting locality characteristics with reconfigurable memory hierarchy for GPGPUs. - Yicong Zhang; Mingyu Wang; Wangguang Wang; Zhiyi Yu (Microelectron. J., 2023)

High-Reliability, Reconfigurable, and Fully Non-volatile Full-Adder Based on SOT-MTJ for Image Processing Applications. - Xing Jin 005; Weichong Chen; Ximing Li 003; Ningyuan Yin; Caihua Wan; Mingkun Zhao; Xiufeng Han; Zhiyi Yu (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Parallel-Prefix Adder in Spin-Orbit Torque Magnetic RAM for High Bit-Width Non-Volatile Computation. - Ximing Li 003; Xing Jin 005; Weichong Chen; Ningyuan Yin; Zhiyi Yu (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A High-Density and Reconfigurable SRAM-Based Digital Compute-In-Memory Macro for Low-Power AI Chips. - Chuanghao Zhang; Mingyu Wang 003; Yangzhan Mai; Chengcheng Tang; Zhiyi Yu (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

TensorCache: Reconstructing Memory Architecture With SRAM-Based In-Cache Computing for Efficient Tensor Computations in GPGPUs. - Yicong Zhang; Mingyu Wang 003; Yangzhan Mai; Zhiyi Yu (IEEE Trans. Very Large Scale Integr. Syst., 2023)

An Efficient Asynchronous Circuits Design Flow with Backward Delay Propagation Constraint. - Lingfeng Zhou; Shanlin Xiao; Huiyao Wang; Jinghai Wang; Zeyang Xu; Bohan Wang; Zhiyi Yu (DATE, 2024)

Sparsespikformer: A Co-Design Framework for Token and Weight Pruning in Spiking Transformer. - Yue Liu; Shanlin Xiao; Bo Li; Zhiyi Yu (ICASSP, 2024)

CCacheSim: A Circuit-Architecture Cross-Level Simulation Framework for SRAM-Based in-Cache Computing System Evaluation. - Baiqing Zhong; Mingyu Wang; Yicong Zhang; Xiaojie Li; Zhiyi Yu (ICCD, 2024)

Energy-Efficient and Fault-Tolerant Sparse Coding for Spiking Neural Networks Accelerator. - Bo Li; Wei Liu; Yue Liu; Xiao Huang; Zhiyi Yu; Shanlin Xiao (ICTA, 2024)

An FPGA-based QDI Asynchronous Circuits Design Methodology. - Guangyao Lin; Jinghai Wang; Zeyang Xu; Zhiyi Yu; Shanlin Xiao (ICTA, 2024)

BafSP: Co-Design of Compute SRAM and Bit-Aware Data Flip Mitigation with In-Memory Sparsity Detection for SpMM. - Xiaojie Li; Mingyu Wang 003; Yangzhan Mai; Yicong Zhang; Baiqing Zhong; Zhiyi Yu (ISVLSI, 2024)

DAW-DMR: Divergence-Aware Warped DMR with Full Error Detection for GPGPU s. - Yukun Wei; Mingyu Wang 003; Haiqiu Huang; Wangguang Wang; Zhiyi Yu (ISVLSI, 2024)

Atomic Cache: Enabling Efficient Fine-Grained Synchronization with Relaxed Memory Consistency on GPGPUs Through In-Cache Atomic Operations. - Yicong Zhang; Mingyu Wang 003; Wangguang Wang; Yangzhan Mai; Haiqiu Huang; Zhiyi Yu (MICRO, 2024)

An Adaptive Re-Read Strategy for Mitigating Temporary Read Errors in 3D-NAND Flash Solid-State Drives. - Ruibin Zhou; Yuhan Wang; Jian Huang; Xinrui Zhang; Xianping Liu; Zhiyi Yu (NVMSA, 2024)

Enhancing aspect-based sentiment analysis with dependency-attention GCN and mutual assistance mechanism. - Jialin Feng; Hong Li; Zhiyi Yu (J. Intell. Inf. Syst., 2024)

Enhancing text classification with attention matrices based on BERT. - Zhiyi Yu; Hong Li; Jialin Feng (Expert Syst. J. Knowl. Eng., 2024)

Contrastive learning for unsupervised sentence embeddings using negative samples with diminished semantics. - Zhiyi Yu; Hong Li; Jialin Feng (J. Supercomput., 2024)

Better-Than-Worst-Case: A Frequency Adaptation Asynchronous RISC-V Core With Vector Extension. - Lingfeng Zhou; Shanlin Xiao; Huiyao Wang; Jinghai Wang; Zeyang Xu; Bohan Wang; Zhiyi Yu (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Low-Power, High-Speed, and Area-Efficient Multiplier Based on the PTL Logic Style. - Wanyuan Pan; Yihe Yu; Chengcheng Tang; Ningyuan Yin; Zhiyi Yu (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

LAC: A Novel Lightweight Asynchronous Controller With Optimized Phase Shift. - Huiyao Wang; Shanlin Xiao; Lingfeng Zhou; Jinghai Wang; Zeyang Xu; Bohan Wang; Zhiyi Yu (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

SC-PLR: An Approximate Spiking Neural Network Accelerator With On-Chip Predictive Learning Rule. - Wei Liu 118; Shanlin Xiao; Yue Liu; Zhiyi Yu (IEEE Trans. Biomed. Circuits Syst., 2024)

Toward Efficient Asynchronous Circuits Design Flow Using Backward Delay Propagation Constraint. - Lingfeng Zhou; Shanlin Xiao; Huiyao Wang; Jinghai Wang; Zeyang Xu; Bohan Wang; Zhiyi Yu (IEEE Trans. Very Large Scale Integr. Syst., 2024)

SCSC: Leveraging Sparsity and Fault-Tolerance for Energy-Efficient Spiking Neural Networks. - Bo Li; Yue Liu; Wei Liu 118; Jinghai Wang; Xiao Huang; Zhiyi Yu; Shanlin Xiao (ASP-DAC, 2025)

FDAIMC: A Fully-Differential Analog In-Memory-Computing for MAC in MRAM with Accuracy Calibration Under Process and Voltage Variation. - Xiangyu Li; Weichong Chen; Ruida Hong; Jinghai Wang; Ningyuan Yin; Zhiyi Yu (DATE, 2025)

A Low-Complexity True Random Number Generation Scheme Using 3D-NAND Flash Memory. - Ruibin Zhou; Jian Huang; Xianping Liu; Yuhan Wang; Xinrui Zhang; Yungen Peng; Zhiyi Yu (DATE, 2025)

A Half-Bit-Per-Cell Strategy for Enhancing Flash Memory Reliability in Harsh Environments. - Ruibin Zhou; Yuhan Wang; Jian Huang; Zecheng Xu; Xianping Liu; Xinrui Zhang; Zhiyi Yu (IRPS, 2025)

A Time-Borrowing Method for High-Performance Bundled-Data Asynchronous Circuits. - Bohan Wang; Zeyang Xu; Lingfeng Zhou; Huiyao Wang; Jinghai Wang; Zhiyi Yu; Shanlin Xiao (ISQED, 2025)

UIC: A unified and scalable chip integrating neuromorphic computation and general purpose processor. - Qiang Zhang 034; Mingyue Cui; Weichong Chen; Yue Liu; Zhiyi Yu (Microelectron. J., 2025)

An End-to-End Bundled-Data Asynchronous Circuits Design Flow: From RTL to GDS. - Jinghai Wang; Shanlin Xiao; Jilong Luo; Bo Li; Lingfeng Zhou; Zhiyi Yu (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Low-Power and Low-Cost AI Processor With Distributed-Aggregated Classification Architecture for Wearable Epilepsy Seizure Detection. - Qiang Zhang 034; Mingyue Cui; Yue Liu; Weichong Chen; Zhiyi Yu (IEEE Trans. Biomed. Circuits Syst., 2025)

CINOC: Computing in Network-On-Chip With Tiled Many-Core Architectures for Large-Scale General Matrix Multiplications. - Yao Qin; Mingyu Wang 003; Jiahua Yan; Tao Lu; Zhiyi Yu (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A Hybrid CAM-SRAM Processing-in-Memory Architecture With Feature Level Sparsity for Attention Mechanisms. - Haiqiu Huang; Mingyu Wang 003; Xiaojie Li; Baiqing Zhong; Zeqi Yang; Tao Lu; Yicong Zhang; Zhiyi Yu (IEEE Trans. Circuits Syst. II Express Briefs, 2025)