A 3.6 TOPS/W Hybrid FP-FXP Deep Learning Processor with Outlier Compensation for Image-to-Image Application. - Zhiyong Li 016; Dongseok Im; Jinsu Lee; Hoi-Jun Yoo (ISCAS, 2021)

An 0.92 mJ/frame High-quality FHD Super-resolution Mobile Accelerator SoC with Hybrid-precision and Energy-efficient Cache. - Zhiyong Li 016; Sangjin Kim; Dongseok Im; Donghyeon Han; Hoi-Jun Yoo (CICC, 2022)

A Low-power and Real-time 3D Object Recognition Processor with Dense RGB-D Data Acquisition in Mobile Platforms. - Dongseok Im; Gwangtae Park; Junha Ryu; Zhiyong Li 016; Sanghoon Kang; Donghyeon Han; Jinsu Lee; Wonhoon Park; Hankyul Kwon; Hoi-Jun Yoo (COOL CHIPS, 2022)

DSPU: A 281.6mW Real-Time Deep Learning-Based Dense RGB-D Data Acquisition with Sensor Fusion and 3D Perception System-on-Chip. - Dongseok Im; Gwangtae Park; Zhiyong Li 016; Junha Ryu; Sanghoon Kang; Donghyeon Han; Jinsu Lee; Wonhoon Park; Hankyul Kwon; Hoi-Jun Yoo (HCS, 2022)

An Efficient High-quality FHD Super-resolution Mobile Accelerator SoC with Hybrid-precision and Energy-efficient Cache. - Zhiyong Li 016; Sangjin Kim; Dongseok Im; Donghyeon Han; Hoi-Jun Yoo (HCS, 2022)

A 161.6 TOPS/W Mixed-mode Computing-in-Memory Processor for Energy-Efficient Mixed-Precision Deep Neural Networks. - Wooyoung Jo; Sangjin Kim; Juhyeong Lee; Soyeon Um; Zhiyong Li 016; Hoi-Jun Yoo (ISCAS, 2022)

DSPU: A 281.6mW Real-Time Depth Signal Processing Unit for Deep Learning-Based Dense RGB-D Data Acquisition with Depth Fusion and 3D Bounding Box Extraction in Mobile Platforms. - Dongseok Im; Gwangtae Park; Zhiyong Li 016; Junha Ryu; Sanghoon Kang; Donghyeon Han; Jinsu Lee; Hoi-Jun Yoo (ISSCC, 2022)

Energy-efficient Dense DNN Acceleration with Signed Bit-slice Architecture. - Dongseok Im; Gwangtae Park; Zhiyong Li 016; Junha Ryu; Hoi-Jun Yoo (CoRR, 2022)

Sibia: Signed Bit-slice Architecture for Dense DNN Acceleration with Slice-level Sparsity Exploitation. - Dongseok Im; Gwangtae Park; Zhiyong Li 016; Junha Ryu; Hoi-Jun Yoo (HPCA, 2023)

A Reconfigurable 1T1C eDRAM-based Spiking Neural Network Computing-In-Memory Processor for High System-Level Efficiency. - Seryeong Kim; Soyeon Kim; Soyeon Um; Sangjin Kim; Zhiyong Li 016; Sangyeob Kim; Wooyoung Jo; Hoi-Jun Yoo (ISCAS, 2023)

DynaPlasia: An eDRAM In-Memory-Computing-Based Reconfigurable Spatial Accelerator with Triple-Mode Cell for Dynamic Resource Switching. - Sangjin Kim; Zhiyong Li 016; Soyeon Um; Wooyoung Jo; Sangwoo Ha; Juhyoung Lee; Sangyeob Kim; Donghyeon Han; Hoi-Jun Yoo (ISSCC, 2023)

Scaling-CIM: An eDRAM-based In-Memory-Computing Accelerator with Dynamic-Scaling ADC for SQNR-Boosting and Layer-wise Adaptive Bit-Truncation. - Sangjin Kim; Soyeon Um; Wooyoung Jo; Jingu Lee; Sangwoo Ha; Zhiyong Li 016; Hoi-Jun Yoo (VLSI Technology and Circuits, 2023)

DSPU: An Efficient Deep Learning-Based Dense RGB-D Data Acquisition With Sensor Fusion and 3-D Perception SoC. - Dongseok Im; Gwangtae Park; Junha Ryu; Zhiyong Li 016; Sanghoon Kang; Donghyeon Han; Jinsu Lee; Wonhoon Park; Hankyul Kwon; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2023)

A Mobile 3-D Object Recognition Processor With Deep-Learning-Based Monocular Depth Estimation. - Dongseok Im; Gwangtae Park; Zhiyong Li 016; Junha Ryu; Sanghoon Kang; Donghyeon Han; Jinsu Lee; Wonhoon Park; Hankyul Kwon; Hoi-Jun Yoo (IEEE Micro, 2023)

An Efficient Deep-Learning-Based Super-Resolution Accelerating SoC With Heterogeneous Accelerating and Hierarchical Cache. - Zhiyong Li 016; Sangjin Kim; Dongseok Im; Donghyeon Han; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2023)

NoPIM: Functional Network-on-Chip Architecture for Scalable High-Density Processing-in-Memory-based Accelerator. - Sangjin Kim; Zhiyong Li 016; Soyeon Um; Wooyoung Jo; Sangwoo Ha; Sangyeob Kim; Hoi-Jun Yoo (COOL CHIPS, 2024)

A Low-Power Neural Graphics System for Instant 3D Modeling and Real-Time Rendering on Mobile AR/VR Devices. - Junha Ryu; Hankyul Kwon; Wonhoon Park; Zhiyong Li 016; Beomseok Kwon; Donghyeon Han; Dongseok Im; Sangyeob Kim; Hyungnam Joo; Minsung Kim; Hoi-Jun Yoo (COOL CHIPS, 2024)

Zero-Shot Structure-Preserving Diffusion Model for High Dynamic Range Tone Mapping. - Ruoxi Zhu; Shusong Xu; Peiye Liu; Sicheng Li 001; Yanheng Lu; Dimin Niu; Zihao Liu; Zihao Meng; Zhiyong Li 016; Xinhua Chen; Yibo Fan (CVPR, 2024)

NeuGPU: A Neural Graphics Processing Unit for Instant Modeling and Real-Time Rendering on Mobile AR/VR Devices. - Junha Ryu; Hankyul Kwon; Wonhoon Park; Zhiyong Li 016; Beomseok Kwon; Donghyeon Han; Dongseok Im; Sangyeob Kim; Hyungnam Joo; Minsung Kim; Hoi-Jun Yoo (HCS, 2024)

20.7 NeuGPU: A 18.5mJ/Iter Neural-Graphics Processing Unit for Instant-Modeling and Real-Time Rendering with Segmented-Hashing Architecture. - Junha Ryu; Hankyul Kwon; Wonhoon Park; Zhiyong Li 016; Beomseok Kwon; Donghyeon Han; Dongseok Im; Sangyeob Kim; Hyungnam Joo; Hoi-Jun Yoo (ISSCC, 2024)

DynaPlasia: An eDRAM In-Memory Computing-Based Reconfigurable Spatial Accelerator With Triple-Mode Cell. - Sangjin Kim; Zhiyong Li 016; Soyeon Um; Wooyoung Jo; Sangwoo Ha; Juhyoung Lee; Sangyeob Kim; Donghyeon Han; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2024)

A 92 fps and 2.56 mJ/Frame Computing-In-Memory-Based Human Pose Estimation Accelerator With Resource-Efficient Macro for Mobile Devices. - Beomseok Kwon; Zhiyong Li 016; Sangjin Kim; Wooyoung Jo; Hoi-Jun Yoo (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Scaling-CIM: eDRAM In-Memory-Computing Accelerator With Dynamic-Scaling ADC and Adaptive Analog Operation. - Sangjin Kim; Soyeon Um; Wooyoung Jo; Jingu Lee; Sangwoo Ha; Zhiyong Li 016; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2024)

NeuGPU: An Energy-Efficient Neural Graphics Processing Unit for Instant Modeling and Real-Time Rendering on Mobile Devices. - Junha Ryu; Hankyul Kwon; Wonhoon Park; Zhiyong Li 016; Beomseok Kwon; Donghyeon Han; Dongseok Im; Sangyeob Kim; Hyungnam Joo; Minsung Kim; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2025)

A Tightly Coupled AI-ISP Vision Processor. - Hao Zhang 126; Sicheng Li 001; Yupeng Gui; Zhiyong Li 016; Shusong Xu; Yanheng Lu; Dimin Niu; Hongzhong Zheng; Yen-Kuang Chen; Yuan Xie 001; Yibo Fan (IEEE Trans. Circuits Syst. Video Technol., 2025)