Hybrid BIST Test Scheduling Based on Defect Probabilities. - Zhiyuan He 002; Gert Jervan; Zebo Peng; Petru Eles (Asian Test Symposium, 2004)

Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment. - Zhiyuan He 002; Gert Jervan; Zebo Peng; Petru Eles (DSD, 2005)

Power constrained and defect-probability driven SoC test scheduling with test set partitioning. - Zhiyuan He 002; Zebo Peng; Petru Eles (DATE, 2006)

A heuristic for thermal-safe SoC test scheduling. - Zhiyuan He 002; Zebo Peng; Petru Eles (ITC, 2007)

Simulation-Driven Thermal-Safe Test Time Minimization for System-on-Chip. - Zhiyuan He 002; Zebo Peng; Petru Eles (ATS, 2008)

Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving. - Zhiyuan He 002; Zebo Peng; Petru Eles; Paul M. Rosinger; Bashir M. Al-Hashimi (J. Electron. Test., 2008)

Thermal-Aware Test Scheduling for Core-Based SoC in an Abort-on-First-Fail Test Environment. - Zhiyuan He 002; Zebo Peng; Petru Eles (DSD, 2009)

Temperature-Aware SoC Test Scheduling Considering Inter-Chip Process Variation. - Nima Aghaee; Zhiyuan He 002; Zebo Peng; Petru Eles (Asian Test Symposium, 2010)

Multi-temperature testing for core-based system-on-chip. - Zhiyuan He 002; Zebo Peng; Petru Eles (DATE, 2010)