A Statistical Current and Delay Model Based on Log-Skew-Normal Distribution for Low Voltage Region. - Peng Cao 002; Jiangping Wu; Zhiyuan Liu 011; Jingjing Guo; Jun Yang 006; Longxing Shi (ACM Great Lakes Symposium on VLSI, 2019)

A Statistical Timing Model for Low Voltage Design Considering Process Variation. - Peng Cao 002; Zhiyuan Liu 011; Jiangping Wu; Jingjing Guo; Jun Yang 006; Longxing Shi (ICCAD, 2019)

A Statistical Timing Model for CMOS Inverter in Near-threshold Region Considering Input Transition Time. - Peng Cao 002; Zhiyuan Liu 011; Bingqian Xu; Jingjing Guo (ICECS, 2019)

Accurate and Efficient Interdependent Timing Model for Flip-Flop in Wide Voltage Region. - Peng Cao 002; Zhiyuan Liu 011; Jingjing Guo; Haoyu Pang; Jiangping Wu; Jun Yang 006 (NEWCAS, 2019)

An Analytical Gate Delay Model in Near/Subthreshold Domain Considering Process Variation. - Peng Cao 002; Zhiyuan Liu 011; Jingjing Guo; Jiangping Wu (IEEE Access, 2019)

Statistical Timing Model for Subthreshold Circuit with Correlated Variation Consideration. - Jingjing Guo; Peng Cao 002; Mengxiao Li; Zhiyuan Liu 011; Jun Yang 006 (ISCAS, 2020)

Semi-Analytical Path Delay Variation Model With Adjacent Gates Decorrelation for Subthreshold Circuits. - Jingjing Guo; Peng Cao 002; Mengxiao Li; Yu Gong; Zhiyuan Liu 011; Geng Bai; Jun Yang 006 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)