Modified Peripheral MRAM Sensing for In-memory Boolean Logic. - Zhong-Jian Bian; Xiaofeng Hong; Juntong Chen; Hao Cai (ASICON, 2021)

In-MRAM Computing Elements with Single-Step Convolution and Fully Connected for BNN/TNN. - Zhong-Jian Bian; Yanan Guo 004; Bo Liu 019; Hao Cai 001 (ICTA, 2021)

Towards Near LLC Speed STT-MRAM Sensing Using Reconfigurable Clock Trimming. - Xiaoyun Tian; Zhong-Jian Bian; Hao Cai (ICTA, 2022)

A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference. - Hao Cai 001; Zhong-Jian Bian; Yaoru Hou; Yongliang Zhou; Jia-Le Cui; Yanan Guo 004; Xiaoyun Tian; Bo Liu 019; Xin Si; Zhen Wang 019; Jun Yang 006; Weiwei Shan (ISSCC, 2023)

Computing in-memory with cascaded spintronic devices for AI edge. - Zhong-Jian Bian; Bo Liu 019; Hao Cai 001 (Comput. Electr. Eng., 2023)