A programmable VLSI architecture for 2-D discrete wavelet transform. - Chien-Yu Chen 001; Zhong-Lan Yang; Tu-Chih Wang; Liang-Gee Chen (ISCAS, 2000)

Hardware-efficient architecture design of tree-depth scanning and multiple quantization scheme for MPEG-4 still texture coding. - Hao-Chieh Chang; Zhong-Lan Yang; Chung-Jr Lian; Liang-Gee Chen (ISCAS (2), 2001)

A Programmable Parallel VLSI Architecture for 2-D Discrete Wavelet Transform. - Chien-Yu Chen 001; Zhong-Lan Yang; Tu-Chih Wang; Liang-Gee Chen (J. VLSI Signal Process., 2001)

Hardware-Efficient Architecture Design for Zerotree Coding in MPEG-4 Still Texture Coder. - Chung-Jr Lian; Zhong-Lan Yang; Hao-Chieh Chang; Liang-Gee Chen (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)