Optimal two level partitioning and loop scheduling for hiding memory latency for DSP applications. - Zhong Wang 004; Michael Kirkpatrick 001; Edwin Hsing-Mean Sha (DAC, 2000)

Combined partitioning and data padding for scheduling multiple loop nests. - Zhong Wang 004; Edwin Hsing-Mean Sha; Xiaobo Hu 001 (CASES, 2001)

Optimal partitioning and balanced scheduling with the maximal overlap of data footprints. - Zhong Wang 004; Edwin Hsing-Mean Sha; Yuke Wang (ACM Great Lakes Symposium on VLSI, 2001)

Scheduling and partitioning for multiple loop nests. - Zhong Wang 004; Qingfeng Zhuge; Edwin Hsing-Mean Sha (ISSS, 2001)

Optimal loop scheduling for hiding memory latency based on two-level partitioning and prefetching. - Zhong Wang 004; Timothy W. O'Neil; Edwin Hsing-Mean Sha (IEEE Trans. Signal Process., 2001)

Minimizing Average Schedule Length under Memory Constraints by Optimal Partitioning and Prefetching. - Zhong Wang 004; Timothy W. O'Neil; Edwin Hsing-Mean Sha (J. VLSI Signal Process., 2001)

Partitioning and Scheduling DSP Applications with Maximal Memory Access Hiding. - Zhong Wang 004; Edwin Hsing-Mean Sha; Yuke Wang (EURASIP J. Adv. Signal Process., 2002)

Register aware scheduling for distributed cache clustered architecture. - Zhong Wang 004; Xiaobo Sharon Hu; Edwin Hsing-Mean Sha (ASP-DAC, 2003)

Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks. - Zhong Wang 004; Xiaobo Sharon Hu (DATE, 2004)

Energy-aware variable partitioning and instruction scheduling for multibank memory architectures. - Zhong Wang 004; Xiaobo Sharon Hu (ACM Trans. Design Autom. Electr. Syst., 2005)