Multi retention level STT-RAM cache designs with a dynamic refresh scheme. - Zhenyu Sun 001; Xiuyuan Bi; Hai (Helen) Li; Weng-Fai Wong; Zhong-Liang Ong; Xiaochun Zhu; Wenqing Wu (MICRO, 2011)

Optimizing the MapReduce framework on Intel Xeon Phi coprocessor. - Mian Lu; Lei Zhang 005; Huynh Phung Huynh; Zhongliang Ong; Yun Liang 001; Bingsheng He; Rick Siow Mong Goh; Richard Huynh (IEEE BigData, 2013)

A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicores. - Jianxing Wang; Yenni Tim; Weng-Fai Wong; Zhong-Liang Ong; Zhenyu Sun 001; Hai Li 001 (ASP-DAC, 2014)

Mapping Streaming Applications onto GPU Systems. - Huynh Phung Huynh; Andrei Hagiescu; Zhong-Liang Ong; Weng-Fai Wong; Rick Siow Mong Goh (IEEE Trans. Parallel Distributed Syst., 2014)

MrPhi: An Optimized MapReduce Framework on Intel Xeon Phi Coprocessors. - Mian Lu; Yun Liang 001; Huynh Phung Huynh; Zhongliang Ong; Bingsheng He; Rick Siow Mong Goh (IEEE Trans. Parallel Distributed Syst., 2015)

Exploiting Sparsity to Accelerate Fully Connected Layers of CNN-Based Applications on Mobile SoCs. - Xinfeng Xie; Dayou Du; Qian Li 027; Yun Liang 001; Wai Teng Tang; Zhongliang Ong; Mian Lu; Huynh Phung Huynh; Rick Siow Mong Goh (ACM Trans. Embed. Comput. Syst., 2018)