Design of four-transistor Pixel for high speed CMOS image. - Yangfan Zhou; Zhongxiang Cao; Quanliang Li; Qi Qin; Nanjian Wu (ASICON, 2011)

7.3 A 1000fps vision chip based on a dynamically reconfigurable hybrid architecture comprising a PE array and self-organizing map neural network. - Cong Shi 003; Jie Yang 033; Ye Han; Zhongxiang Cao; Qi Qin; Liyuan Liu; Nanjian Wu; Zhihua Wang 001 (ISSCC, 2014)

A high speed 1000 fps CMOS image sensor with low noise global shutter pixels. - Yangfan Zhou; Zhongxiang Cao; Qi Qin; Quanliang Li; Cong Shi 003; Nanjian Wu (Sci. China Inf. Sci., 2014)

A 1000 fps Vision Chip Based on a Dynamically Reconfigurable Hybrid Architecture Comprising a PE Array Processor and Self-Organizing Map Neural Network. - Cong Shi 003; Jie Yang 033; Ye Han; Zhongxiang Cao; Qi Qin; Liyuan Liu; Nanjian Wu; Zhihua Wang 001 (IEEE J. Solid State Circuits, 2014)

A low power global shutter pixel with extended FD voltage swing range for large format high speed CMOS image sensor. - Yangfan Zhou; Zhongxiang Cao; Ye Han; Quanliang Li; Cong Shi 003; Runjiang Dou; Qi Qin; Jian Liu 021; Nanjian Wu (Sci. China Inf. Sci., 2015)

A 256×256 time-of-flight image sensor based on center-tap demodulation pixel structure. - Zhe Chen; Shan Di; Zhongxiang Cao; Qi Qin; Fei Ji; Liyuan Liu; Nanjian Wu (Sci. China Inf. Sci., 2016)