Parasitic Parameters Impacts Investigation on Soft Error Rate by a Circuit Level Framework. - Weiguang Sheng; Zhongyuan Zhao 004; Zhigang Mao (PRDC, 2015)

Resource-saving compile flow for coarse-grained reconfigurable architectures. - Zhongyuan Zhao 004; Weiguang Sheng; Naifeng Jing; Weifeng He; Zhigang Mao (ReConFig, 2015)

Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memory. - Naifeng Jing; Taozhong Li; Zhongyuan Zhao 004; Wei Jin 004; Yanan Sun 003; Weifeng He; Zhigang Mao (FPT, 2016)

A static-placement, dynamic-issue framework for CGRA loop accelerator. - Zhongyuan Zhao 004; Weiguang Sheng; Weifeng He; Zhigang Mao; Zhaoshi Li (DATE, 2017)

Optimizing the data placement and transformation for multi-bank CGRA computing system. - Zhongyuan Zhao 004; Yantao Liu; Weiguang Sheng; Tushar Krishna; Qin Wang 009; Zhigang Mao (DATE, 2018)

MBSS: A General Paradigm for Static Schedule for Nested Loops with Dynamic Loop Boundary on CGRAs. - Shuai Xie; Zhongyuan Zhao 004; Weiguang Sheng; Qin Wang 009; Zhigang Mao (ReConFig, 2018)

mRNA: Enabling Efficient Mapping Space Exploration for a Reconfiguration Neural Accelerator. - Zhongyuan Zhao 004; Hyoukjun Kwon; Sachit Kuhar; Weiguang Sheng; Zhigang Mao; Tushar Krishna (ISPASS, 2019)

Towards Higher Performance and Robust Compilation for CGRA Modulo Scheduling. - Zhongyuan Zhao 004; Weiguang Sheng; Qin Wang 009; Wenzhi Yin; Pengfei Ye; Jinchao Li; Zhigang Mao (IEEE Trans. Parallel Distributed Syst., 2020)

Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable Architecture. - Yuge Chen; Zhongyuan Zhao 004; Jianfei Jiang 001; Guanghui He; Zhigang Mao; Weiguang Sheng (DATE, 2021)

A Tensor Processing Framework for CPU-Manycore Heterogeneous Systems. - Lin Cheng; Peitian Pan; Zhongyuan Zhao 004; Krithik Ranjan; Jack Weber; Bandhav Veluri; Seyed Borna Ehsani; Max Ruttenberg; Dai Cheol Jung; Preslav Ivanov; Dustin Richmond; Michael B. Taylor; et al. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

An Intermediate Language for General Sparse Format Customization. - Jie Liu 072; Zhongyuan Zhao 004; Zijian Ding; Benjamin Brock; Hongbo Rong; Zhiru Zhang (IEEE Comput. Archit. Lett., 2023)

Scalable, Programmable and Dense: The HammerBlade Open-Source RISC-V Manycore. - Dai Cheol Jung; Max Ruttenberg; Paul Gao 001; Scott Davidson 004; Daniel Petrisko; Kangli Li; Aditya K. Kamath; Lin Cheng; Shaolin Xie; Peitian Pan; Zhongyuan Zhao 004; Zichao Yue; et al. (ISCA, 2024)

UniSparse: An Intermediate Language for General Sparse Format Customization. - Jie Liu 072; Zhongyuan Zhao 004; Zijian Ding; Benjamin Brock; Hongbo Rong; Zhiru Zhang (Proc. ACM Program. Lang., 2024)

Vesper: A Versatile Sparse Linear Algebra Accelerator With Configurable Compute Patterns. - Hanchen Jin; Zichao Yue; Zhongyuan Zhao 004; Yixiao Du; Chenhui Deng; Nitish Srivastava; Zhiru Zhang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)