An offset cancellation technique for SRAM sense amplifier based on relation of the delay and offset. - Yue Zhao; Jinkai Wang; Zhongzhen Tong; Xiulong Wu; Chunyu Peng; Wenjuan Lu; Qiang Zhao 007; Zhiting Lin (Microelectron. J., 2022)

In-Memory Multibit Multiplication Based on Bitline Shifting. - Jin Zhang 036; Zhiting Lin; Xiulong Wu; Zhongzhen Tong; Chunyu Peng; Wenjuan Lu; Qiang Zhao 007; Hongbiao Wu; Junning Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Configurable Memory With a Multilevel Shared Structure Enabling In-Memory Computing. - Yue Zhao; Zhiting Lin; Xiulong Wu; Qiang Zhao 007; Wenjuan Lu; Chunyu Peng; Zhongzhen Tong; Junning Chen (IEEE Trans. Very Large Scale Integr. Syst., 2022)

In Situ Storing 8T SRAM-CIM Macro for Full-Array Boolean Logic and Copy Operations. - Zhiting Lin; Zhongzhen Tong; Fangming Wang; Jin Zhang 036; Yue Zhao; Peng Sun; Tian Xu; Cheng Zhang; Xingwei Li; Xiulong Wu; Wenjuan Lu; Chunyu Peng; et al. (IEEE J. Solid State Circuits, 2023)

A Fully Digital SRAM-Based Four-Layer In-Memory Computing Unit Achieving Multiplication Operations and Results Store. - Zhiting Lin; Shaoying Zhang; Qian Jin; Jianping Xia; Yunwei Liu; Kefeng Yu; Jian Zheng; Xiaoming Xu; Xing Fan; Ke Li; Zhongzhen Tong; Xiulong Wu; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2023)

In-Memory Transposable Multibit Multiplication Based on Diagonal Symmetry Weight Block. - Zhongzhen Tong; Yue Zhao; Jin Zhang 036; Zhiting Lin; Xiaoyang Lin; Xiulong Wu (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Configurable in-memory computing architecture based on dual-port SRAM. - Yue Zhao; Yunlong Liu; Jian Zheng; Zhongzhen Tong; Xin Wang; Runru Yu; Xiulong Wu; Yongliang Zhou; Chunyu Peng; Wenjuan Lu; Qiang Zhao 007; Zhiting Lin (Microelectron. J., 2024)

A High Throughput In-MRAM-Computing Scheme Using Hybrid p-SOT-MTJ/GAA-CNTFET. - Zhongzhen Tong; Yilin Xu; Yunlong Liu; Xinrui Duan; Hao Tang; Suteng Zhao; Chenghang Li; Zhiting Lin; Xiulong Wu; Zhaohao Wang; Xiaoyang Lin (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A Charge-Domain Compute-In-Memory Macro With Cell-Embedded DA Conversion and Two-Stage AD Conversion for Bit-Scalable MAC Operation. - Kaili Zhang; Zhongzhen Tong; Xinxin Liang; Chengzhi Wang; You Wang 002; Yue Zhang 010; Weisheng Zhao; Lang Zeng; Deming Zhang (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Computing In-Memory Multibit Multiplication Based on Decoupling and In-Array Storing. - Jin Zhang 036; Zhongzhen Tong; Hao Wang; Xin Wang; Qiang Zhao 007; Jian Zhou; Jiaqun Wang; Zhiting Lin; Xiulong Wu (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

BSTCIM: A Balanced Symmetry Ternary Fully Digital In-MRAM Computing Macro for Energy Efficiency Neural Network. - Zhongzhen Tong; Chenghang Li; Chao Wang 094; Suteng Zhao; Qianyong Peng; Zhenyu Yan; Siqi Zhang; Daming Zhou; Zhaohao Wang; Xiaoyang Lin; Weisheng Zhao (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Approximate SOT-MRAM for Neural Network Acceleration with Superior Read Performance. - Yulong Qiu; Chao Wang 094; Zhongzhen Tong; Siyuan Cheng 021; Yueting Li; Zhaohao Wang (ISCAS, 2025)

A Novel Radiation-Hardened, Speed and Power Optimized Nonvolatile Latch for Aerospace Applications. - Shixing Li; Chenyi Wang; Zhongzhen Tong; Chao Wang 094; Bi Wang 002; Zhaohao Wang (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

In-MRAM Computing Based on Complementary-Sensing Time-Based Readout Circuit Using Hybrid VGSOT-MTJ/GAA-CNTFET. - Zhongzhen Tong; Sifan Sun; Kaili Zhang; Chenghang Li; Daming Zhou; Zhaohao Wang; Xiaoyang Lin; Weisheng Zhao (IEEE Trans. Circuits Syst. II Express Briefs, 2025)