A Memetic Approach for Nanoscale Hybrid Circuit Cell Mapping. - Zhufei Chu; Yinshui Xia; William N. N. Hung; Lun-Yao Wang; Xiaoyu Song (DSD, 2010)

Cell Mapping for Nanohybrid Circuit Architecture Using Genetic Algorithm. - Zhufei Chu; Yinshui Xia; Lun-Yao Wang (J. Comput. Sci. Technol., 2012)

Voltage Drop Aware Power Pad Assignment and Floorplanning for Multi-voltage SoC Designs. - Zhufei Chu; Yinshui Xia; Lun-Yao Wang; Jian Wang (CAD/Graphics, 2013)

Low Power State Assignment Algorithm for FSMs Considering Peak Current Optimization. - Lun-Yao Wang; Zhufei Chu; Yinshui Xia (J. Comput. Sci. Technol., 2013)

Level shifter planning for timing constrained multi-voltage SoC floorplanning. - Zhufei Chu; Yinshui Xia; Lun-Yao Wang (ACM Great Lakes Symposium on VLSI, 2014)

Efficient nonrectangular shaped voltage island aware floorplanning with nonrandomized searching engine. - Zhufei Chu; Yinshui Xia; Lun-Yao Wang; Jian Wang (Microelectron. J., 2014)

Efficient power pad assignment for multi-voltage SoC and its application in floorplanning. - Zhufei Chu; Yinshui Xia; Lun-Yao Wang; Jian Wang (Int. J. Circuit Theory Appl., 2016)

Multi-supply voltage (MSV) driven SoC floorplanning for fast design convergence. - Zhufei Chu; Yinshui Xia; Lun-Yao Wang (Integr., 2016)

Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains. - Zhufei Chu; Xifan Tang; Mathias Soeken; Ana Petkovska; Grace Zgheib; Luca Gaetano Amarù; Yinshui Xia; Paolo Ienne; Giovanni De Micheli; Pierre-Emmanuel Gaillardon (ACM Great Lakes Symposium on VLSI, 2017)

Functional decomposition using majority. - Zhufei Chu; Mathias Soeken; Yinshui Xia; Giovanni De Micheli (ASP-DAC, 2018)

Area Optimization of MPRM Circuits Using Approximate Computing. - Qiuhong Ying; Lun-Yao Wang; Zhufei Chu; Yinshui Xia (ASICON, 2019)

Structural rewriting in XOR-majority graphs. - Zhufei Chu; Mathias Soeken; Yinshui Xia; Lun-Yao Wang; Giovanni De Micheli (ASP-DAC, 2019)

Exact Synthesis of Boolean Functions in Majority-of-Five Forms. - Zhufei Chu; Winston Haaswijk; Mathias Soeken; Yinshui Xia; Lun-Yao Wang; Giovanni De Micheli (ISCAS, 2019)

Multi-objective algebraic rewriting in XOR-majority graphs. - Zhufei Chu; Lei Shi; Lun-Yao Wang; Yinshui Xia (Integr., 2019)

Through-Silicon Via-Based Capacitor and Its Application in LDO Regulator Design. - Libo Qian; Kefang Qian; Xitao He; Zhufei Chu; Yidie Ye; Shi Ge 001; Yinshui Xia (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A High-Performance Design of Generalized Pipeline Cellular Array. - Zhufei Chu; Huiming Tian; Zeqiang Li; Yinshui Xia; Lun-Yao Wang (IEEE Comput. Archit. Lett., 2020)

Advanced Functional Decomposition Using Majority and Its Applications. - Zhufei Chu; Mathias Soeken; Yinshui Xia; Lun-Yao Wang; Giovanni De Micheli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

An Efficient Demultiplexer Design in Quantum-dot Cellular Automata. - Jianguo Ni; Zhufei Chu (ASICON, 2021)

Design of Majority Logic Based 4-bit Approximate Subtractors and its Application in Divider. - Chuanhe Shang; Zhufei Chu (ASICON, 2021)

MinSC: An Exact Synthesis-Based Method for Minimal-Area Stochastic Circuits under Relaxed Error Bound. - Xuan Wang; Zhufei Chu; Weikang Qian (ICCAD, 2021)

Inversion Optimization Strategy Based on Primitives with Complement Attributes. - Huiming Tian; Zhufei Chu (J. Comput. Sci. Technol., 2021)

Defect-Tolerant Mapping of CMOL Circuit Targeting Delay Optimization. - Xiaojing Zha; Yinshui Xia; Shang-Luan Xie; Zhufei Chu (J. Comput. Sci. Technol., 2021)

BCD Adder Designs Based on Three-Input XOR and Majority Gates. - Zhufei Chu; Zeqiang Li; Yinshui Xia; Lunyao Wang; Weiqiang Liu 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

The prediction of the quality of results in Logic Synthesis using Transformer and Graph Neural Networks. - Chenghao Yang; Yinshui Xia; Zhufei Chu (CoRR, 2022)

Stochastic circuit synthesis via satisfiability. - Xiang He; Zhufei Chu (Integr., 2022)

Logic Synthesis Optimization Sequence Tuning Using RL-Based LSTM and Graph Isomorphism Network. - Chenghao Yang; Yinshui Xia; Zhufei Chu; Xiaojing Zha (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Efficient Design of Majority-Logic-Based Approximate Arithmetic Circuits. - Zhufei Chu; Chuanhe Shang; Tingting Zhang; Yinshui Xia; Lunyao Wang; Weiqiang Liu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2022)

2022 roadmap on neuromorphic devices and applications research in China. - Qing Wan; Changjin Wan; Huaqiang Wu; Yuchao Yang 001; Xiaohe Huang; Peng Zhou 021; Lin Chen; Tian-Yu Wang; Yi Li 049; Kanhao Xue; Yu-Hui He; Xiangshui Miao; et al. (Neuromorph. Comput. Eng., 2022)

Exact Synthesis Based on Semi-Tensor Product Circuit Solver. - Hongyang Pan; Zhufei Chu (DATE, 2023)

DeepGate2: Functionality-Aware Circuit Representation Learning. - Zhengyuan Shi; Hongyang Pan; Sadaf Khan; Min Li 019; Yi Liu; Junhua Huang; Hui-Ling Zhen; Mingxuan Yuan; Zhufei Chu; Qiang Xu 001 (ICCAD, 2023)

A Semi-Tensor Product Based All Solutions Boolean Satisfiability Solver. - Hongyang Pan; Zhufei Chu (J. Comput. Sci. Technol., 2023)

An efficient circuit-based SAT solver and its application in logic equivalence checking. - Kunmei Hu; Zhufei Chu (Microelectron. J., 2023)

FPGA EDA - Design Principles and Implementation - Kaihui Tu; Xifan Tang; Cunxi Yu; Lana Josipovic; Zhufei Chu (Springer, 2024)

A Semi-Tensor Product based Circuit Simulation for SAT-sweeping. - Hongyang Pan; Ruibing Zhang; Yinshui Xia; Lunyao Wang; Fan Yang 001; Xuan Zeng 001; Zhufei Chu (DATE, 2024)

Area-Aware Logic Mapping for MAGIC based In-Memory Computing. - Jiaxiang Pan; Zhufei Chu (SMACD, 2024)

Large circuit models: opportunities and challenges. - Lei Chen; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Ru Huang 001; Yu Huang 005; Sadaf Khan; Min Li; Xingquan Li; Yu Li; Yun Liang 001; et al. (Sci. China Inf. Sci., 2024)

Erratum to: Large circuit models: opportunities and challenges. - Lei Chen; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Ru Huang 001; Yu Huang 005; Sadaf Khan; Min Li; Xingquan Li; Yu Li; Yun Liang 001; et al. (Sci. China Inf. Sci., 2024)

Solid-state non-volatile memories based on vdW heterostructure-based vertical-transport ferroelectric field-effect transistors. - Qiyu Yang; Zheng-Dong Luo; Fei Xiao; Junpeng Zhang; Dawei Zhang; Dongxin Tan; Xuetao Gan; Yan Liu; Zhufei Chu; Yinshui Xia; Genquan Han (Sci. China Inf. Sci., 2024)

The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models. - Lei Chen 002; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Yu Huang 005; Sadaf Khan; Min Li 019; Xingquan Li; Yun Liang 001; Yibo Lin; Jinwei Liu; et al. (CoRR, 2024)

EDA-Driven Preprocessing for SAT Solving. - Zhengyuan Shi; Tiebing Tang; Sadaf Khan; Hui-Ling Zhen; Mingxuan Yuan; Zhufei Chu; Qiang Xu 001 (CoRR, 2024)

OpenLS-DGF: An Adaptive Open-Source Dataset Generation Framework for Machine Learning Tasks in Logic Synthesis. - Liwei Ni; Rui Wang; Miao Liu; Xingyu Meng; Xiaoze Lin; Junfeng Liu; Guojie Luo; Zhufei Chu; Weikang Qian; Xiaoyan Yang; Biwei Xie; Xingquan Li; et al. (CoRR, 2024)

Artificial neural network models for metal-ferroelectric-insulator-semiconductor ferroelectric tunnel junction memristor. - Tiancheng Li; Erping Li 001; Huali Duan; Zhufei Chu; Jian Wang; Wenchao Chen (Microelectron. J., 2024)

Semi-Tensor Product-Based Exact Synthesis for Logic Rewriting. - Hongyang Pan; Yinshui Xia; Lunyao Wang; Zhufei Chu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

DynamicSAT: Dynamic Configuration Tuning for SAT Solving. - Zhengyuan Shi; Wentao Jiang; Xindi Zhang; Jin Luo; Yun Liang 001; Zhufei Chu; Qiang Xu 001 (CP, 2025)

ELMap: Area-Driven LUT Mapping with $k$-LUT Network Exact Synthesis. - Hongyang Pan; Keren Zhu 001; Fan Yang 001; Zhufei Chu; Xuan Zeng 001 (DATE, 2025)

Ferroelectrically gated two-dimensional bismuth oxyselenides for strain-invariant flexible synaptic thin-film transistors. - Jie Wen; Fei Xiao; Zheng-Dong Luo; Dongxin Tan; Xuetao Gan; Dawei Zhang; Zhufei Chu; Yinshui Xia; Yan Liu; Genquan Han (Sci. China Inf. Sci., 2025)

Implication logic synthesis and optimization methods for memristor-based logic circuits. - Tingting Liu; Zhufei Chu (Microelectron. J., 2025)

DeepCell: Multiview Representation Learning for Post-Mapping Netlists. - Zhengyuan Shi; Chengyu Ma; Ziyang Zheng; Lingfeng Zhou; Hongyang Pan; Wentao Jiang; Fan Yang 001; Xiaoyan Yang; Zhufei Chu; Qiang Xu 001 (CoRR, 2025)

DeepCircuitX: A Comprehensive Repository-Level Dataset for RTL Code Understanding, Generation, and PPA Analysis. - Zeju Li; Changran Xu; Zhengyuan Shi; Zedong Peng; Yi Liu; Yunhao Zhou; Lingfeng Zhou; Chengyu Ma; Jianyuan Zhong; Xi Wang; Jieru Zhao; Zhufei Chu; et al. (CoRR, 2025)

Mixed Structural Choice Operator: Enhancing Technology Mapping with Heterogeneous Representations. - Zhang Hu; Hongyang Pan; Yinshui Xia; Lunyao Wang; Zhufei Chu (CoRR, 2025)

ForgeEDA: A Comprehensive Multimodal Dataset for Advancing EDA. - Zhengyuan Shi; Zeju Li; Chengyu Ma; Yunhao Zhou; Ziyang Zheng; Jiawei Liu 006; Hongyang Pan; Lingfeng Zhou; Kezhi Li; Jiaying Zhu; Lingwei Yan; Zhiqiang He; et al. (CoRR, 2025)