An O(nlogn) time algorithm for optimal buffer insertion. - Weiping Shi; Zhuo Li 001 (DAC, 2003)

CodSim – A Combined Delay Fault Simulator. - Wangqi Qiu; Xiang Lu; Zhuo Li 001; D. M. H. Walker; Weiping Shi (DFT, 2003)

Process variation dimension reduction based on SVD. - Zhuo Li 001; Xiang Lu; Weiping Shi (ISCAS (4), 2003)

A Circuit Level Fault Model for Resistive Opens and Bridges. - Zhuo Li 001; Xiang Lu; Wangqi Qiu; Weiping Shi; D. M. H. Walker (VTS, 2003)

A circuit level fault model for resistive bridges. - Zhuo Li 001; Xiang Lu; Wangqi Qiu; Weiping Shi; D. M. H. Walker (ACM Trans. Design Autom. Electr. Syst., 2003)

Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost. - Weiping Shi; Zhuo Li 001; Charles J. Alpert (ASP-DAC, 2004)

PARADE: PARAmetric Delay Evaluation under Process Variation. - Xiang Lu; Zhuo Li 001; Wangqi Qiu; D. M. H. Walker; Weiping Shi (ISQED, 2004)

K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits. - Wangqi Qiu; Jing Wang 006; D. M. H. Walker; Divya Reddy; Zhuo Li 001; Weiping Shi; Hari Balachandran (ITC, 2004)

A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide. - Xiang Lu; Zhuo Li 001; Wangqi Qiu; D. M. H. Walker; Weiping Shi (MTV, 2004)

A Statistical Fault Coverage Metric for Realistic Path Delay Faults. - Wangqi Qiu; Xiang Lu; Jing Wang 006; Zhuo Li 001; D. M. H. Walker; Weiping Shi (VTS, 2004)

Making fast buffer insertion even faster via approximation techniques. - Zhuo Li 001; Cliff C. N. Sze; Charles J. Alpert; Jiang Hu; Weiping Shi (ASP-DAC, 2005)

A More Effective CEFF. - Sani R. Nassif; Zhuo Li 001 (ISQED, 2005)

Longest-path selection for delay test under process variation. - Xiang Lu; Zhuo Li 001; Wangqi Qiu; D. M. H. Walker; Weiping Shi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

A fast algorithm for optimal buffer insertion. - Weiping Shi; Zhuo Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Fast interconnect optimization. - Zhuo Li 001 (2005)

An O(mn) time algorithm for optimal buffer insertion of nets with m sinks. - Zhuo Li 001; Weiping Shi (ASP-DAC, 2006)

Buffer insertion in large circuits with constructive solution search techniques. - Mandar Waghmode; Zhuo Li 001; Weiping Shi (DAC, 2006)

A new RLC buffer insertion algorithm. - Zhanyuan Jiang; Shiyan Hu 001; Jiang Hu; Zhuo Li 001; Weiping Shi (ICCAD, 2006)

An O(bn2) time algorithm for optimal buffer insertion with b buffer types. - Zhuo Li 001; Weiping Shi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects. - Nancy Ying Zhou; Zhuo Li 001; Yuxin Tian; Weiping Shi; Frank Liu 001 (ASP-DAC, 2007)

Fast Capacitance Extraction in Multilayer, Conformal and Embedded Dielectric using Hybrid Boundary Element Method. - Nancy Ying Zhou; Zhuo Li 001; Weiping Shi (DAC, 2007)

Probabilistic Congestion Prediction with Partial Blockages. - Zhuo Li 001; Charles J. Alpert; Stephen T. Quay; Sachin S. Sapatnekar; Weiping Shi (ISQED, 2007)

The nuts and bolts of physical synthesis. - Charles J. Alpert; Shrirang K. Karandikar; Zhuo Li 001; Gi-Joon Nam; Stephen T. Quay; Haoxing Ren; Cliff C. N. Sze; Paul G. Villarrubia; Mehmet Can Yildiz (SLIP, 2007)

An O(bn^2) Time Algorithm for Optimal Buffer Insertion with b Buffer Types - Zhuo Li 001; Weiping Shi (CoRR, 2007)

Techniques for Fast Physical Synthesis. - Charles J. Alpert; Shrirang K. Karandikar; Zhuo Li 001; Gi-Joon Nam; Stephen T. Quay; Haoxing Ren; Cliff C. N. Sze; Paul G. Villarrubia; Mehmet Can Yildiz (Proc. IEEE, 2007)

Fast Algorithms for Slew-Constrained Minimum Cost Buffering. - Shiyan Hu 001; Charles J. Alpert; Jiang Hu; Shrirang K. Karandikar; Zhuo Li 001; Weiping Shi; Chin Ngai Sze (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Wire Sizing for Non-Tree Topology. - Zhuo Li 001; Nancy Ying Zhou; Weiping Shi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Path smoothing via discrete optimization. - Michael D. Moffitt; David A. Papa; Zhuo Li 001; Charles J. Alpert (DAC, 2008)

A polynomial time approximation scheme for timing constrained minimum cost layer assignment. - Shiyan Hu 001; Zhuo Li 001; Charles J. Alpert (ICCAD, 2008)

Pyramids: an efficient computational geometry-based approach for timing-driven placement. - Tao Luo 002; David A. Papa; Zhuo Li 001; Chin Ngai Sze; Charles J. Alpert; David Z. Pan (ICCAD, 2008)

SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes. - Rouwaida Kanj; Rajiv V. Joshi; Zhuo Li 001; Jente B. Kuang; Hung C. Ngo; Nancy Ying Zhou; Weiping Shi; Sani R. Nassif (ISLPED, 2008)

Fast interconnect synthesis with layer assignment. - Zhuo Li 001; Charles J. Alpert; Shiyan Hu 001; Tuhin Muhmud; Stephen T. Quay; Paul G. Villarrubia (ISPD, 2008)

A Root-Finding Method for Assessing SRAM Stability. - Rouwaida Kanj; Zhuo Li 001; Rajiv V. Joshi; Frank Liu 001; Sani R. Nassif (ISQED, 2008)

RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm. - David A. Papa; Tao Luo 002; Michael D. Moffitt; Chin Ngai Sze; Zhuo Li 001; Gi-Joon Nam; Charles J. Alpert; Igor L. Markov (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Buffer Insertion Basics. - Jiang Hu; Zhuo Li 001; Shiyan Hu 001 (Handbook of Algorithms for Physical Design Automation, 2008)

A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion. - Shiyan Hu 001; Zhuo Li 001; Charles J. Alpert (DAC, 2009)

A faster approximation scheme for timing driven minimum cost layer assignment. - Shiyan Hu 001; Zhuo Li 001; Charles J. Alpert (ISPD, 2009)

The impact of BEOL lithography effects on the SRAM cell performance and yield. - Nancy Ying Zhou; Rouwaida Kanj; Kanak Agarwal 001; Zhuo Li 001; Rajiv V. Joshi; Sani R. Nassif; Weiping Shi (ISQED, 2009)

A Fully Polynomial-Time Approximation Scheme for Timing-Constrained Minimum Cost Layer Assignment. - Shiyan Hu 001; Zhuo Li 001; Charles J. Alpert (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Detecting tangled logic structures in VLSI netlists. - Tanuj Jindal; Charles J. Alpert; Jiang Hu; Zhuo Li 001; Gi-Joon Nam; Charles B. Winn (DAC, 2010)

New placement prediction and mitigation techniques for local routing congestion. - Taraneh Taghavi; Zhuo Li 001; Charles J. Alpert; Gi-Joon Nam; Andrew D. Huber; Shyam Ramji (ICCAD, 2010)

What makes a design difficult to route. - Charles J. Alpert; Zhuo Li 001; Michael D. Moffitt; Gi-Joon Nam; Jarrod A. Roy; Gustavo E. Téllez (ISPD, 2010)

Ultra-fast interconnect driven cell cloning for minimizing critical path delay. - Zhuo Li 001; David A. Papa; Charles J. Alpert; Shiyan Hu 001; Weiping Shi; Cliff C. N. Sze; Nancy Ying Zhou (ISPD, 2010)

ITOP: integrating timing optimization within placement. - Natarajan Viswanathan; Gi-Joon Nam; Jarrod A. Roy; Zhuo Li 001; Charles J. Alpert; Shyam Ramji; Chris Chu (ISPD, 2010)

2011 TAU power grid simulation contest: Benchmark suite and results. - Zhuo Li 001; Raju Balasubramanian; Frank Liu 001; Sani R. Nassif (ICCAD, 2011)

The ISPD-2011 routability-driven placement contest and benchmark suite. - Natarajan Viswanathan; Charles J. Alpert; Cliff C. N. Sze; Zhuo Li 001; Gi-Joon Nam; Jarrod A. Roy (ISPD, 2011)

Quantifying academic placer performance on custom designs. - Samuel I. Ward; David A. Papa; Zhuo Li 001; Cliff N. Sze; Charles J. Alpert; Earl E. Swartzlander Jr. (ISPD, 2011)

Physical Synthesis with Clock-Network Optimization for Large Systems on Chips. - David A. Papa; Charles J. Alpert; Cliff C. N. Sze; Zhuo Li 001; Natarajan Viswanathan; Gi-Joon Nam; Igor L. Markov (IEEE Micro, 2011)

CAD for Gigascale SoC Design and Verification Solutions. - Shiyan Hu 001; Zhuo Li 001; Yangdong Deng (VLSI Design, 2011)

Shedding Physical Synthesis Area Bloat. - Nancy Ying Zhou; Charles J. Alpert; Zhuo Li 001; Cliff N. Sze; Louise Trevillyan (VLSI Design, 2011)

Yield estimation via multi-cones. - Rouwaida Kanj; Rajiv V. Joshi; Zhuo Li 001; Jerry Hayes; Sani R. Nassif (DAC, 2012)

Guiding a physical design closure system to produce easier-to-route designs with more predictable timing. - Zhuo Li 001; Charles J. Alpert; Gi-Joon Nam; Cliff C. N. Sze; Natarajan Viswanathan; Nancy Y. Zhou (DAC, 2012)

The DAC 2012 routability-driven placement contest and benchmark suite. - Natarajan Viswanathan; Charles J. Alpert; Cliff C. N. Sze; Zhuo Li 001; Yaoguang Wei (DAC, 2012)

GLARE: global and local wiring aware routability evaluation. - Yaoguang Wei; Cliff C. N. Sze; Natarajan Viswanathan; Zhuo Li 001; Charles J. Alpert; Lakshmi N. Reddy; Andrew D. Huber; Gustavo E. Téllez; Douglas Keller; Sachin S. Sapatnekar (DAC, 2012)

Placement: Hot or Not? - Charles J. Alpert; Zhuo Li 001; Gi-Joon Nam; Chin Ngai Sze; Natarajan Viswanathan; Samuel I. Ward (ICCAD, 2012)

Opening: Introduction to CAD contest at ICCAD 2012: CAD contest. - Iris Hui-Ru Jiang; Zhuo Li 001; Yih-Lang Li (ICCAD, 2012)

2012 TAU power grid simulation contest: Benchmark suite and results. - Zhuo Li 001; Raju Balasubramanian; Frank Liu 001; Sani R. Nassif (ICCAD, 2012)

ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suite. - Natarajan Viswanathan; Charles J. Alpert; Cliff C. N. Sze; Zhuo Li 001; Yaoguang Wei (ICCAD, 2012)

Keep it straight: teaching placement how to better handle designs with datapaths. - Samuel I. Ward; Myung-Chul Kim; Natarajan Viswanathan; Zhuo Li 001; Charles J. Alpert; Earl E. Swartzlander Jr.; David Z. Pan (ISPD, 2012)

$O(mn)$ Time Algorithm for Optimal Buffer Insertion of Nets With $m$ Sinks. - Zhuo Li 001; Nancy Ying Zhou; Weiping Shi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Routing congestion estimation with real design constraints. - Wen-Hao Liu 001; Yaoguang Wei; Cliff C. N. Sze; Charles J. Alpert; Zhuo Li 001; Yih-Lang Li; Natarajan Viswanathan (DAC, 2013)

CATALYST: planning layer directives for effective design closure. - Yaoguang Wei; Zhuo Li 001; Cliff C. N. Sze; Shiyan Hu 001; Charles J. Alpert; Sachin S. Sapatnekar (DATE, 2013)

ICCAD-2013 CAD contest in mask optimization and benchmark suite. - Shayak Banerjee; Zhuo Li 001; Sani R. Nassif (ICCAD, 2013)

The overview of 2013 CAD contest at ICCAD. - Iris Hui-Ru Jiang; Zhuo Li 001; Hwei-Tseng Wang; Natarajan Viswanathan (ICCAD, 2013)

ICCAD-2013 CAD contest in placement finishing and benchmark suite. - Myung-Chul Kim; Natarajan Viswanathan; Zhuo Li 001; Charles J. Alpert (ICCAD, 2013)

Clock power minimization using structured latch templates and decision tree induction. - Samuel I. Ward; Natarajan Viswanathan; Nancy Y. Zhou; Cliff C. N. Sze; Zhuo Li 001; Charles J. Alpert; David Z. Pan (ICCAD, 2013)

Structure-Aware Placement Techniques for Designs With Datapaths. - Samuel I. Ward; Myung-Chul Kim; Natarajan Viswanathan; Zhuo Li 001; Charles J. Alpert; Earl E. Swartzlander Jr.; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Pacman: driving nonuniform clock grid loads for low-skew robust clock network. - Nancy Y. Zhou; Phillip J. Restle; Joseph N. Palumbo; Joseph N. Kozhaya; Haifeng Qian; Zhuo Li 001; Charles J. Alpert; Cliff C. N. Sze (SLIP, 2014)

Techniques for scalable and effective routability evaluation. - Yaoguang Wei; Cliff C. N. Sze; Natarajan Viswanathan; Zhuo Li 001; Charles J. Alpert; Lakshmi N. Reddy; Andrew D. Huber; Gustavo E. Téllez; Douglas Keller; Sachin S. Sapatnekar (ACM Trans. Design Autom. Electr. Syst., 2014)

Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography. - Bei Yu 001; Xiaoqing Xu; Jhih-Rong Gao; Yibo Lin; Zhuo Li 001; Charles J. Alpert; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Stitch aware detailed placement for multiple E-beam lithography. - Yibo Lin; Bei Yu 001; Yi Zou; Zhuo Li 001; Charles J. Alpert; David Z. Pan (Integr., 2017)

Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees. - Charles J. Alpert; Wing-Kai Chow; Kwangsoo Han; Andrew B. Kahng; Zhuo Li 001; Derong Liu 002; Sriram Venkatesh (ISPD, 2018)

MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes. - Yibo Lin; Bei Yu 001; Xiaoqing Xu; Jhih-Rong Gao; Natarajan Viswanathan; Wen-Hao Liu 001; Zhuo Li 001; Charles J. Alpert; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Conference Report From The 57th Design Automation Conference. - Zhuo Li 001 (IEEE Des. Test, 2020)

Invited: The Future of Functional ECO Automation and Logical Equivalence Checking for Advanced Digital Design Flows. - Zhuo Li 001; David Stratman (ISPD, 2025)