FPGA Acceleration for Computational Glass-Free Displays. - Zhuolun He; Guojie Luo (FPGA, 2017)

FPGA-Based Real-Time Super-Resolution System for Ultra High Definition Videos. - Zhuolun He; Hanxian Huang; Ming Jiang 001; Yuanchao Bai; Guojie Luo (FCCM, 2018)

Learn to Floorplan through Acquisition of Effective Local Search Heuristics. - Zhuolun He; Yuzhe Ma; Lu Zhang; Peiyu Liao; Ngai Wong 001; Bei Yu 001; Martin D. F. Wong (ICCD, 2020)

Understanding Graphs in EDA: From Shallow to Deep Learning. - Yuzhe Ma; Zhuolun He; Wei Li 159; Lu Zhang; Bei Yu 001 (ISPD, 2020)

HOTCAKE: Higher Order Tucker Articulated Kernels for Deeper CNN Compression. - Rui Lin; Ching-Yun Ko; Zhuolun He; Cong Chen 003; Yuan Cheng; Hao Yu 001; Graziano Chesi; Ngai Wong 001 (CoRR, 2020)

Deep Model Compression and Inference Speedup of Sum-Product Networks on Tensor Trains. - Ching-Yun Ko; Cong Chen 003; Zhuolun He; Yuke Zhang; Kim Batselier; Ngai Wong 001 (IEEE Trans. Neural Networks Learn. Syst., 2020)

Physical Synthesis for Advanced Neural Network Processors. - Zhuolun He; Peiyu Liao; Siting Liu 002; Yuzhe Ma; Yibo Lin; Bei Yu 001 (ASP-DAC, 2021)

Graph Learning-Based Arithmetic Block Identification. - Zhuolun He; Ziyi Wang 010; Chen Bai; Haoyu Yang; Bei Yu 001 (ICCAD, 2021)

Functionality matters in netlist representation learning. - Ziyi Wang 010; Chen Bai; Zhuolun He; Guangliang Zhang; Qiang Xu 001; Tsung-Yi Ho; Bei Yu 001; Yu Huang 005 (DAC, 2022)

X-Check: CPU-Accelerated Design Rule Checking via Parallel Sweepline Algorithms. - Zhuolun He; Yuzhe Ma; Bei Yu 001 (ICCAD, 2022)

AutoGraph: Optimizing DNN Computation Graph for Parallel GPU Kernel Execution. - Yuxuan Zhao 001; Qi Sun 002; Zhuolun He; Yang Bai; Bei Yu 001 (AAAI, 2023)

OpenDRC: An Efficient Open-Source Design Rule Checking Engine with Hierarchical GPU Acceleration. - Zhuolun He; Yihang Zuo; Jiaxi Jiang; Haisheng Zheng; Yuzhe Ma; Bei Yu 001 (DAC, 2023)

Efficient Design Rule Checking with GPU Acceleration. - Wei Zhong; Zhenhua Feng; Zhuolun He; Weimin Wang; Yuzhe Ma; Bei Yu 001 (DATE, 2023)

Invited Paper: Heterogeneous Acceleration for Design Rule Checking. - Zhuolun He; Bei Yu 001 (ICCAD, 2023)

AlphaSyn: Logic Synthesis Optimization with Efficient Monte Carlo Tree Search. - Zehua Pei; Fangzhou Liu; Zhuolun He; Guojin Chen; Haisheng Zheng; Keren Zhu 001; Bei Yu 001 (ICCAD, 2023)

Efficient Arithmetic Block Identification With Graph Learning and Network-Flow. - Ziyi Wang 010; Zhuolun He; Chen Bai; Haoyu Yang; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Efficient Super-Resolution System With Block-Wise Hybridization and Quantized Winograd on FPGA. - Bizhao Shi; Jiaxi Zhang 001; Zhuolun He; Xuechao Wei; Sicheng Li 001; Guojie Luo; Hongzhong Zheng; Yuan Xie 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

LSTP: A Logic Synthesis Timing Predictor. - Haisheng Zheng; Zhuolun He; Fangzhou Liu; Zehua Pei; Bei Yu 001 (ASPDAC, 2024)

PDRC: Package Design Rule Checking via GPU-Accelerated Geometric Intersection Algorithms for Non-Manhattan Geometry. - Jiaxi Jiang; Lancheng Zou; Wenqian Zhao; Zhuolun He; Tinghuan Chen; Bei Yu 001 (DAC, 2024)

Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs. - Yuan Pu 001; Fangzhou Liu; Yu Zhang 189; Zhuolun He; Yibo Lin; Kai-Yuan Chao; Bei Yu 001 (DAC, 2024)

CBTune: Contextual Bandit Tuning for Logic Synthesis. - Fangzhou Liu; Zehua Pei; Ziyang Yu 001; Haisheng Zheng; Zhuolun He; Tinghuan Chen; Bei Yu 001 (DATE, 2024)

Parameter-Efficient Sparsity Crafting from Dense to Mixture-of-Experts for Instruction Tuning on General Tasks. - Haoyuan Wu; Haisheng Zheng; Zhuolun He; Bei Yu 001 (EMNLP, 2024)

Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA. - Yuan Pu 001; Zhuolun He; Tairu Qiu; Haoyuan Wu; Bei Yu 001 (ICCAD, 2024)

Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs. - Siting Liu 002; Jiaxi Jiang; Zhuolun He; Ziyi Wang 010; Yibo Lin; Bei Yu 001; Martin D. F. Wong (ISPD, 2024)

Large Language Models for EDA: Future or Mirage? - Zhuolun He; Bei Yu 001 (ISPD, 2024)

IncreMacro: Incremental Macro Placement Refinement. - Yuan Pu 001; Tinghuan Chen; Zhuolun He; Chen Bai; Haisheng Zheng; Yibo Lin; Bei Yu 001 (ISPD, 2024)

ChatEDA: A Large Language Model Powered Autonomous Agent for EDA. - Haoyuan Wu; Zhuolun He; Xinyun Zhang; Xufeng Yao; Su Zheng; Haisheng Zheng; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Efficient OpAmp Adaptation for Zoom Attention to Golden Contexts. - Haoyuan Wu; Rui Ming; Haisheng Zheng; Zhuolun He; Bei Yu 001 (ACL (1), 2025)

iRw: An Intelligent Rewriting. - Haisheng Zheng; Haoyuan Wu; Zhuolun He; Yuzhe Ma; Bei Yu 001 (DATE, 2025)

HeLO: A Heterogeneous Logic Optimization Framework by Hierarchical Clustering and Graph Learning. - Yuan Pu 001; Fangzhou Liu; Zhuolun He; Keren Zhu 001; Rongliang Fu; Ziyi Wang 010; Tsung-Yi Ho; Bei Yu 001 (ISPD, 2025)

Divergent Thoughts toward One Goal: LLM-based Multi-Agent Collaboration System for Electronic Design Automation. - Haoyuan Wu; Haisheng Zheng; Zhuolun He; Bei Yu 001 (NAACL (Long Papers), 2025)

Large Language Models for EDA: From Assistants to Agents. - Zhuolun He; Yuan Pu 001; Haoyuan Wu; Yuhan Qiu; Tairu Qiu; Bei Yu 001 (Found. Trends Electron. Des. Autom., 2025)

FGNN2: A Powerful Pretraining Framework for Learning the Logic Functionality of Circuits. - Ziyi Wang 010; Chen Bai; Zhuolun He; Guangliang Zhang; Qiang Xu 001; Tsung-Yi Ho; Yu Huang 005; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Architect of the Bits World: Masked Autoregressive Modeling for Circuit Generation Guided by Truth Table. - Haoyuan Wu; Haisheng Zheng; Shoubo Hu; Zhuolun He; Bei Yu 001 (CoRR, 2025)

UniMoCo: Unified Modality Completion for Robust Multi-Modal Embeddings. - Jiajun Qin; Yuan Pu 001; Zhuolun He; Seunggeun Kim; David Z. Pan; Bei Yu 001 (CoRR, 2025)

ToTRL: Unlock LLM Tree-of-Thoughts Reasoning Potential through Puzzles Solving. - Haoyuan Wu; Xueyi Chen; Rui Ming; Jilong Gao; Shoubo Hu; Zhuolun He; Bei Yu 001 (CoRR, 2025)

On-Policy Optimization with Group Equivalent Preference for Multi-Programming Language Understanding. - Haoyuan Wu; Rui Ming; Jilong Gao; Hangyu Zhao; Xueyi Chen; Yikai Yang; Haisheng Zheng; Zhuolun He; Bei Yu 001 (CoRR, 2025)

EasyMRC: Efficient Mask Rule Checking via Representative Edge Sampling. - Jiahao Xu; Zhuolun He; Shuo Yin; Yuan Pu 001; Wenjian Yu; Bei Yu 001 (ACM Trans. Design Autom. Electr. Syst., 2025)

IncreMacro: Incremental Macro Placement Refinement. - Yuan Pu 001; Tinghuan Chen; Zhuolun He; Jiajun Qin; Chen Bai; Haisheng Zheng; Yibo Lin; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)