Yield optimization for low power current controlled current conveyor. - Zia Abbas; Marat Yakupov; Mauro Olivieri; Andreas Ripp; Gunter Strube (SBCCI, 2012)

Design centering/yield optimization of power aware band pass filter based on CMOS current controlled current conveyor (CCCII+). - Zia Abbas; Mauro Olivieri; Marat Yakupov; Andreas Ripp (Microelectron. J., 2013)

Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells. - Zia Abbas; Mauro Olivieri (Microelectron. J., 2014)

A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs. - Zia Abbas; Antonio Mastrandrea; Mauro Olivieri (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Optimal transistor sizing for maximum yield in variation-aware standard cell design. - Zia Abbas; Mauro Olivieri (Int. J. Circuit Theory Appl., 2016)

LEADER: Leakage Currents Estimation Technique for Aging Degradation Aware 16 nm CMOS Circuits. - Zia Abbas; Andleeb Zahra; Mauro Olivieri (VDAT, 2018)

Voltage Level Adapter Design for High Voltage Swing Applications in CMOS Differential Amplifier. - Ashfakh Ali; Arpan Jain; Zia Abbas (VDAT, 2018)

Optimal Transistor Sizing of Full-Adder Block to Reduce Standby Leakage Power. - Prateek Gupta; Shubham Kumar; Zia Abbas (VDAT, 2018)

A Highly Accurate Machine Learning Approach to Modelling PVT Variation Aware Leakage Power in FinFET Digital Circuits. - Shirisha Gourishetty; Harshini Mandadapu; Andleeb Zahra; Zia Abbas (APCCAS, 2019)

A Memetic Algorithm Based PVT Variation-Aware Robust Transistor Sizing Scheme for Power-Delay Optimal Digital Standard Cell Design. - Mohammed Salman Ahmed 001; Zia Abbas (ICCD, 2019)

PVT Variations Aware Robust Transistor Sizing for Power-Delay Optimal CMOS Digital Circuit Design. - Prateek Gupta; Shirisha Gourishetty; Harshini Mandadapu; Zia Abbas (ISCAS, 2019)

A High PSRR, Stable CMOS Current Reference using Process Insensitive TC of Resistance for Wide Temperature Applications. - Arpan Jain; Ashfakh Ali; Sai Kiran; Zia Abbas (ISCAS, 2019)

Robust Transistor Sizing for Improved Performances in Digital Circuits using Optimization Algorithms. - Prateek Gupta; Harshini Mandadapu; Shirisha Gourishetty; Zia Abbas (ISQED, 2019)

Statistical Variation Aware Leakage and Total Power Estimation of 16 nm VLSI Digital Circuits Based on Regression Models. - Deepthi Amuru; Andleeb Zahra; Zia Abbas (VDAT, 2019)

A 47nW, 0.7-3.6V wide Supply Range, Resistor Based Temperature Sensor for IoT Applications. - Ashfakh Ali; Sai Kiran; Arpan Jain; Zia Abbas (VLSI-SoC, 2019)

ATM: Approximate Toom-Cook Multiplication for Speech Processing Applications. - Mohammed Salman Ahmed 002; Deepthi Amuru; Zia Abbas (ISCAS, 2020)

An Efficient Gradient Boosting Approach for PVT Aware Estimation of Leakage Power and Propagation Delay in CMOS/FinFET Digital Cells. - Deepthi Amuru; Mohammed Salman Ahmed 002; Zia Abbas (ISCAS, 2020)

67ppm/°C, 66nA PVT Invariant Curvature Compensated Current Reference for Ultra-Low Power Applications. - Balaji Yadav Battu; Mounika Kelam; Adithya Bathi; Zia Abbas (ISCAS, 2020)

Low Quiescent Current, Capacitor-Less LDO with Adaptively Biased Power Transistors and Load Aware Feedback Resistance. - Balaji Yadav Battu; Mounika Kelam; Koushik De; Zia Abbas (ISCAS, 2020)

A Compact, Power Efficient, Self-Adaptive and PVT Invariant CMOS Relaxation Oscillator. - Mounika Kelam; Balaji Yadav Battu; Zia Abbas (ISVLSI, 2020)

A Sub-nW, 8T Current Reference Consuming Constant Power w.r.t Process & Temperature. - Ashfakh Ali; Abhishek Pullela; Arpan Jain; Zia Abbas (MWSCAS, 2020)

3.75ppm/°C, -91dB PSRR, 27nW, 0.9V PVT Invariant Voltage Reference for Implantable Biomedical Applications. - Mounika Kelam; Balaji Yadav Battu; Zia Abbas (VLSID, 2020)

Algorithm Driven Power-Timing Optimization Methodology for CMOS Digital Circuits Considering PVTA Variations. - Hema Sai Kalluru; Prasenjit Saha; Andleeb Zahra; Zia Abbas (ISCAS, 2021)

A 419pW Process-Invariant Temperature Sensor for Ultra-Low Power Microsystems. - Abhishek Pullela; Ashfakh Ali; Arpan Jain; Adithya Banthi; Zia Abbas (ISCAS, 2021)

Low Power PVT-Aware Transistor Sizing and Approximate Design Generation for Standard Cells Using Swarm Intelligence. - Prasenjit Saha; Salman Ahmed; Hema Sai Kalluru; Zia Abbas (ISCAS, 2021)

PVT and Aging Degradation Invariant Automated Optimization Approach for CMOS Low-Power High-Performance VLSI Circuits. - Hema Sai Kalluru; Prasenjit Saha; Andleeb Zahra; Zia Abbas (ISQED, 2021)

A 0.85V Supply, High PSRR CMOS Voltage Reference without Resistor and Amplifier for Ultra-Low Power Applications. - Ashutosh Pathy; Adithya Banthi; Zia Abbas (MWSCAS, 2021)

A 443pW Accumulation-Mode Gate-Leakage Based Bandgap Reference for IoT Applications. - Abhishek Pullela; Ashfakh Ali; Sushanth Reddy; Arpan Jain; Zia Abbas (MWSCAS, 2021)

Transistor Sizing based PVT-Aware Low Power Optimization using Swarm Intelligence. - Prasenjit Saha; Hema Sai Kalluru; Zia Abbas (VLSID, 2021)

A 156pW Gate-Leakage Based Voltage/Current Reference for Low-Power IoT Systems. - Abhishek Pullela; Ashfakh Ali; Arpan Jain; Inhee Lee 001; Zia Abbas (ISCAS, 2022)

Fast and efficient ResNN and Genetic optimization for PVT aware performance enhancement in digital circuits. - Kushagra Agarwal; Aryamaan Jain; Deepthi Amuru; Zia Abbas (VLSI-DAT, 2022)

A 180o Phase Shift Biasing Technique for Realizing High PSRR in Low Power Temperature Sensors. - Arpan Jain; Abhishek Pullela; Ashfakh Ali; Zia Abbas (VLSID, 2022)

Implementation of TRNG with SHA-3 for hardware security. - Annapurna Kamadi; Zia Abbas (Microelectron. J., 2022)

A 9.5nW, 0.55V Supply, CMOS Current Reference for Low Power Biomedical Applications. - Samriddhi Agarwal; Ashutosh Pathy; Zia Abbas (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Design of Approximate Full Adders for Error Resilient Applications. - Deepthi Amuru; Andleeb Zahra; Varnika Karakuram; Zia Abbas (ICCA, 2023)

A High PSRR CMOS Voltage and Current Reference in One Circuit Without Amplifier for Low Power Applications. - Ashutosh Pathy; Andleeb Zahra; Amir Ahmad; Zia Abbas (ICM, 2023)

A Label-Free Low-Cost Radio Frequency Driven Noninvasive Lab-on-Chip System for Creatinine Detection. - Swarnim Sinha; Andleeb Zahra; Imran Siddiqui; Pawan Kumar 001; Alimpan Modak; Prabhakar Bhimalapuram; Tapan K. Sau; Syed Azeemuddin; Zia Abbas (ICST, 2023)

Design and Fabrication of Microfluidic Chip for Temperature Control Applications in Biomedical. - Andleeb Zahra; Giampiero de Cesare; Domenico Caputo; Nicola Lovecchio; Prabhakar Bhimalapuram; Syed Azeemuddin; Zia Abbas (ICST, 2023)

An 18.5nW, 62.9dB PSRR, Switched-Capacitor Bandgap Voltage Reference using Low Power Clock Generator Circuit for Biomedical Applications. - Samriddhi Agarwal; Shameer Basha Yerragudi; Naveen Dasari; Inhee Lee 001; Zia Abbas (ISCAS, 2023)

A 162nW, 0.845pJ/step Resistance-to-Digital Converter for Miniature Battery-Powered Sensing Systems. - Arnab Dey; Inhee Lee 001; Ashfakh Ali; Arpan Jain; Abhishek Pullela; Zia Abbas (ISCAS, 2023)

A 2.3nW Gate-Leakage Based Sub-Bandgap Voltage Reference with Line Sensitivity of 0.0066%/V from -40°C to 150°C for Low-Power IoT Systems. - Arnab Dey; Bharadwaj Subramaniam; Ashfakh Ali; Bhartipudi Sahishnavi; Abhishek Pullela; Zia Abbas (ISCAS, 2023)

A 7 nW, 1 kHz, -40-170°C Relaxation Oscillator with Switch-Leakage Compensation for Low-Power High-Temperature IoT Systems. - Ashfakh Huluvallay; Abhishek Pullela; Ehab A. Hamed; Arpan Jain; Naveen Dasari; Zia Abbas; Inhee Lee 001 (ISCAS, 2023)

A 0.5V, pico-watt, 0.06%/V / 0.03%/V low supply sensitive current/voltage reference without using amplifiers and resistors. - Bhartipudi Sahishnavi; Sampath Kumar; Ashfakh Ali; Arnab Dey; Inhee Lee 001; Zia Abbas (ISCAS, 2023)

Design and Analysis of Low Power 20 GHz Colpitts VCO with FoM of 196.26 dBc/Hz. - Srayan Sankar Chatterjee; Arpit Sahni; Harikrishna Kambham; Zia Abbas; Abhishek Srivastava 002 (MWSCAS, 2023)

A 37nW, All-in-One Trim-Free Voltage/Current Reference Without Using Resistors and Amplifiers. - Chetan Mittal; Arnab Dey; Ashfakh Ali; Khanh M. Le; Zia Abbas (MWSCAS, 2023)

A 250pA, Gate-Leakage Based Trimming Free Current Reference, from -55°C to 150°C for Lower Power IoT Applications. - Abhinav Vajrala; Dheekshith Akula; Arnab Dey; Khanh M. Le; Zia Abbas (MWSCAS, 2023)

Approximate Toom-Cook FFT with sparsity aware error tuning in a shared memory architecture. - Mohammed Salman Ahmed 002; Md. Kalesha; Andleeb Zahra; Zia Abbas (Integr., 2023)

AI/ML algorithms and applications in VLSI design and technology. - Deepthi Amuru; Andleeb Zahra; Harsha V. Vudumula; Pavan K. Cherupally; Sushanth R. Gurram; Amir Ahmad; Zia Abbas (Integr., 2023)

A Single-Point, Auto-Calibration Technique For PTAT/CTAT Resistance Based Current References. - Arpan Jain; Ashfakh Ali; Dheekshith Akula; Abhishek Pullela; Zia Abbas (ISCAS, 2024)

MetaCirc: A Meta-learning Approach for Statistical Leakage Estimation Improvement in Digital Circuits. - Nouduru Venkata Raghavendra; Deepthi Amuru; Zia Abbas (ISCAS, 2024)

An inductor-less, cost-effective On-chip CMOS VNA for bio-molecule detection. - Bhartipudi Sahishnavi; Samriddhi Agarwal; Shameer Basha Yerragudi; Naveen Dasari; Andleeb Zahra; Prabhakar Bhimalapuram; Syed Azeemuddin; Zia Abbas (ISCAS, 2024)

Enhancing ML model accuracy for Digital VLSI circuits using diffusion models: A study on synthetic data generation. - Prasha Srivastava; Pawan Kumar 001; Zia Abbas (ISCAS, 2024)

A Trim-Free PVT Invariant Current Reference with 0.48% Process Inaccuracy Using VTH Tracking Approach. - Vishnu Kuncham; Jalluri Ram Gopal; V. S. S. Pradhith; Aniketh Atmakuri; Chetan Mittal; Khanh M. Le; Zia Abbas (MWSCAS, 2024)

A 0.6V, 13nW, 0.0012%/V Line Sensitivity PVT - Invariant Voltage Reference Without Using Resistors and Amplifiers. - Chetan Mittal; Jalluri Ramgopal; Khanh M. Le; Zia Abbas (MWSCAS, 2024)

A Process and Temperature Compensation Technique for Ring-VCO in Charge-Pump PLL. - Mehul Kumar Saraswat; Rajesh Mahadev; Shameer Basha Yerragudi; Khanh M. Le; Zia Abbas (MWSCAS, 2024)

Design and Optimization of Robust Process Monitors. - Shiva Sharma; Koushik De; Bhartipudi Sahishnavi; Khanh M. Le; Zia Abbas (MWSCAS, 2024)

A 0.8-V, 593-pA Trim-free Duty-cycled All CMOS Current Reference for Ultra-Low Power IoT Applications. - Chetan Mittal; Arnab Dey; Anubhab Banerjee; Ashfakh Ali; Zia Abbas (VLSID, 2024)

Qualitative data augmentation for performance prediction in VLSI circuits. - Prasha Srivastava; Pawan Kumar 001; Zia Abbas (Integr., 2024)

A 275 pW, 0.5 V supply insensitive gate-leakage based current/voltage reference circuit for a wide temperature range of -55 to 100 °C without using amplifiers and resistors. - Bhartipudi Sahishnavi; Arnab Dey; Anubhab Banerjee; Andleeb Zahra; Zia Abbas (Microelectron. J., 2024)

Transfer Learning Enabled Modeling Paradigm for PVT-aware Circuit Performance Estimation. - Deepthi Amuru; Raja Mavullu Vechalapu; Zia Abbas (ACM Trans. Design Autom. Electr. Syst., 2024)

A Theoretical Study of the Representational Power of Weighted Randomised Univariate Regression Tree Ensembles. - Amir Ahmad; Sami M. Halawani; Ajay Kumar 003; Arshad Hashmi; Mutasem Jarrah; Abdul Rafey Ahmad; Zia Abbas (J. Inf. Knowl. Manag., 2024)

Zero-shot Learning in Performance Prediction of Digital VLSI Circuits. - Deepthi Amuru; Zia Abbas (ISCAS, 2025)

Towards Designing a Unified DNN Architecture for Analog and Mixed-Signal Circuit Characterization. - Deepthi Amuru; Chetan Mittal; Zia Abbas (ISCAS, 2025)

C-Arch: Chained Architecture towards Foundation Modeling of CMOS/FinFET Circuit Designs. - Ritwik Basyas Goswami; Mohammad Rehan Akhtar; Andleeb Zahra; Zia Abbas (ISCAS, 2025)

A bidirectional frequency detector independent of input transition density for a wide-tuning range applications. - Abhinav Vajrala; Rajesh Mahadev; Santosh Yachareni; Zia Abbas (ISCAS, 2025)

Low-Power Voltage Reference: Review & Progress. - Abhishek Pullela; Ashfakh Huluvallay; Arpan Jain; Zia Abbas; Inhee Lee 001 (VTS, 2025)

Randomized processes to create diverse models for One-class classifier ensembles. - Deepthi Amuru; Amir Ahmad; Zia Abbas (Appl. Soft Comput., 2025)