Clock-Wirelength-Driven Detailed Placement. - Ziang Ge; Yikai Liu; Jindong Zhou; Pingqiang Zhou (ACM Great Lakes Symposium on VLSI, 2025)

Inductance-aware Clock Network Synthesis Considering Hierarchical Interconnects in 3D ICs. - Jindong Zhou; Ziang Ge; Chenbo Xi; Pingqiang Zhou (ACM Great Lakes Symposium on VLSI, 2025)