A Hybrid CPU+GPU Working-Set Dictionary. - Ziaul Choudhury; Suresh Purini; Shiva Rama Krishna (ISPDC, 2016)

Synthesizing Power and Area Efficient Image Processing Pipelines on FPGAs using Customized Bit-widths. - Vinamra Benara; Sahithi Rampalli; Ziaul Choudhury; Suresh Purini; Uday Bondhugula (CoRR, 2018)

Bitwidth customization in image processing pipelines using interval analysis and SMT solvers. - Suresh Purini; Vinamra Benara; Ziaul Choudhury; Uday Bondhugula (CC, 2020)

Accelerating Local Laplacian Filters on FPGAs. - Shashwat Khandelwal; Ziaul Choudhury; Shashwat Shrivastava; Suresh Purini (FPL, 2020)

FPGA Accelerator for Stereo Vision using Semi-Global Matching through Dependency Relaxation. - Shashwat Shrivastava; Ziaul Choudhury; Shashwat Khandelwal; Suresh Purini (FPL, 2020)

Accuracy Configurable FPGA Implementation of Harris Corner Detection. - Shivani Maurya; Ziaul Choudhury; Suresh Purini (ISVLSI, 2022)

An FPGA Overlay for CNN Inference with Fine-grained Flexible Parallelism. - Ziaul Choudhury; Shashwat Shrivastava; Lavanya Ramapantulu; Suresh Purini (ACM Trans. Archit. Code Optim., 2022)

A Unified Programmable Edge Matrix Processor for Deep Neural Networks and Matrix Algebra. - Biji George; Om Ji Omer; Ziaul Choudhury; Anoop V; Sreenivas Subramoney (ACM Trans. Embed. Comput. Syst., 2022)

FlowPix: Accelerating Image Processing Pipelines on an FPGA Overlay using a Domain Specific Compiler. - Ziaul Choudhury; Anish Gulati; Suresh Purini (ACM Trans. Archit. Code Optim., 2023)