Design and Implementation of a High-Speed Reconfigurable Modular Arithmetic Unit. - Wei Li 131; Zibin Dai; Tao Chen 047; Tao Meng; Xuan S. Yang (APPT, 2007)

The Research and Implementation of Reconfigurable Processor Architecture for Block Cipher Processing. - Zibin Dai; Wei Li 131; Xiaohui Yang; Tao Chen 047; Qiao Ren (ICESS, 2008)

Research and Implementation of a High-Speed Reconfigurable A5 Algorithm. - Wei Li 131; Zibin Dai; Longmei Nan (PACIIA (2), 2008)

The Research of NULL Convention Logic Circuit Computing Model Targeted at Block Cipher Processing. - Yalei Cui; Zibin Dai (IAS, 2009)

Design and application of reusable SoC verification platform. - Lulu Feng; Zibin Dai; Wei Li 131; Jianlei Cheng (ASICON, 2011)

Research on design of a reconfigurable parallel structure targeted at LFSR. - Wei Li 131; Xuan Yang; Zibin Dai (ASICON, 2011)

Research on reconfigurable multiplier unit based on GF[(28)]4 field of symmetric cryptography. - Jianbo Xu; Zibin Dai; Yang Xuan; Yang Su (ASICON, 2011)

Design and Implementation of Configurable LFSR Instructions Targeted at Stream Cipher Processing. - Zibin Dai; Longmei Nan; Xuan S. Yang; Xiaonan Li (J. Circuits Syst. Comput., 2013)

Study and implementation of cluster hierarchical memory system of multicore cryptographic processor. - Junwei Li; Zibin Dai; Wei Li 131; Tao Chen 047; Yufei Zhu (ASICON, 2015)

Fast Parallel Extract-Shift and Parallel Deposit-Shift in General-Purpose Processors. - Wei Li 131; Zhongxiang Chang; Xiao Feng; Zibin Dai (UIC/ATC/ScalCom, 2015)

A High-Throughput Processor for Dual-Field Elliptic Curve Cryptography with Power Analysis Resistance. - Wei Li 131; Xiaoyang Zeng; Xiao Feng; Zibin Dai (UIC/ATC/ScalCom, 2015)

An area-efficient interconnection network for coarse-grain reconfigurable cryptographic array. - Tongzhou Qu; Zibin Dai; Longmei Nan; Wei Li 131; Anqi Yin (ASICON, 2017)

RC6 architecture-adaptive implementation for coarse-grained reconfiguration array. - Anqi Yin; Zibin Dai; Longmei Nan; Wei Li 131 (ASICON, 2017)

A highly efficient reconfigurable rotation unit based on an inverse butterfly network. - Chao Ma; Zibin Dai; Wei Li 131; Hai-juan Zang (Frontiers Inf. Technol. Electron. Eng., 2017)

A single-supply sub-threshold level shifter with an internal supply feedback loop for multi-voltage applications. - Longmei Nan; Xiaoyang Zeng; Wei Li 131; Zhouchuang Wang; Zibin Dai (IEICE Electron. Express, 2018)

An Efficient ASIC Implementation of Public Key Cryptography Algorithm SM2 Based on Module Arithmetic Logic Unit. - Danyang Yang; Zibin Dai; Wei Li 131; Tao Chen 047 (ASICON, 2019)

PVHArray: An Energy-Efficient Reconfigurable Cryptographic Logic Array With Intelligent Mapping. - Yiran Du; Wei Li 131; Zibin Dai; Longmei Nan (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A Cost-Sensitive Golden Chip-Free Hardware Trojan Detection Using Principal Component Analysis and Naïve Bayes Classification Algorithm. - Yanjiang Liu; Xianzhao Xia; Jingxin Zhong; Pengfei Guo; Chunsheng Zhu; Zibin Dai (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022)

A Performance Model for Reconfigurable Block Cipher Array Utilizing Amdahl's Law. - Tongzhou Qu; Zibin Dai; Yanjiang Liu; Lin Chen; Xianzhao Xia (IEICE Trans. Inf. Syst., 2022)

A Comprehensive Evaluation of Integrated Circuits Side-Channel Resilience Utilizing Three-Independent-Gate Silicon Nanowire Field Effect Transistors-Based Current Mode Logic. - Yanjiang Liu; Jiaji He; Haocheng Ma; Tongzhou Qu; Zibin Dai (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A Low-Overhead and High-Security Cryptographic Circuit Design Utilizing the TIGFET-Based Three-Phase Single-Rail Pulse Register against Side-Channel Attacks. - Yanjiang Liu; Tongzhou Qu; Zibin Dai (ACM Trans. Design Autom. Electr. Syst., 2022)

MA-GRNN:a high-efficient modeling attack approach utilizing generalized regression neural network for XOR arbiter physical unclonable functions. - Yanjiang Liu; Gaofeng Huang; Junwei Li; Pengfei Guo; Chunsheng Zhu; Zibin Dai (IEICE Electron. Express, 2023)

Extending the classical side-channel analysis framework to access-driven cache attacks. - Pengfei Guo; Yingjian Yan; Fan Zhang 010; Chunsheng Zhu; Lichao Zhang; Zibin Dai (Comput. Secur., 2023)

CBDC-PUF: A Novel Physical Unclonable Function Design Framework Utilizing Configurable Butterfly Delay Chain Against Modeling Attack. - Yanjiang Liu; Junwei Li; Tongzhou Qu; Zibin Dai (ACM Trans. Design Autom. Electr. Syst., 2023)

R/B-SecArch: A strong isolated SoC architecture based on red/black concept for secure and efficient cryptographic services. - Pengfei Guo; Yingjian Yan; Zhongyi Zhao; Lichao Zhang; Chunsheng Zhu; Zibin Dai (Microelectron. J., 2023)

RGMU: A High-flexibility and Low-cost Reconfigurable Galois Field Multiplication Unit Design Approach for CGRCA. - Danping Jiang; Zibin Dai; Yanjiang Liu; Zongren Zhang (ACM Trans. Design Autom. Electr. Syst., 2024)

CRM_BF: A Low-Overhead, High-Efficient and Reconfigurable Operation Unit Design Approach Using the Customized Reed-Muller Unit For Boolean Functions of Sequence Cipher Algorithms. - Zhaoxu Zhou; Zihang Huang; Junwei Li; Yanjiang Liu; Zibin Dai (ACM Trans. Design Autom. Electr. Syst., 2025)