Comprehensive Benchmarking of Binary Neural Networks on NVM Crossbar Architectures. - Ruirong Huang; Zichao Yue; Caroline Huang; Janarbek Matai; Zhiru Zhang (CoRR, 2023)

Less is More: Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits. - Chenhui Deng; Zichao Yue; Cunxi Yu; Gokce Sarar; Ryan Carey; Rajeev Jain; Zhiru Zhang (DAC, 2024)

A Comprehensive Evaluation of FPGA-Based Spatial Acceleration of LLMs. - Hongzheng Chen; Jiahao Zhang; Yixiao Du; Shaojie Xiang; Zichao Yue; Niansong Zhang; Yaohui Cai; Zhiru Zhang (FPGA, 2024)

Polynormer: Polynomial-Expressive Graph Transformer in Linear Time. - Chenhui Deng; Zichao Yue; Zhiru Zhang (ICLR, 2024)

Scalable, Programmable and Dense: The HammerBlade Open-Source RISC-V Manycore. - Dai Cheol Jung; Max Ruttenberg; Paul Gao 001; Scott Davidson 004; Daniel Petrisko; Kangli Li; Aditya K. Kamath; Lin Cheng; Shaolin Xie; Peitian Pan; Zhongyuan Zhao 004; Zichao Yue; et al. (ISCA, 2024)

Understanding the Potential of FPGA-based Spatial Acceleration for Large Language Model Inference. - Hongzheng Chen; Jiahao Zhang; Yixiao Du; Shaojie Xiang; Zichao Yue; Niansong Zhang; Yaohui Cai; Zhiru Zhang (ACM Trans. Reconfigurable Technol. Syst., 2025)

Graph Learning at Scale: Characterizing and Optimizing Pre-Propagation GNNs. - Zichao Yue; Chenhui Deng; Zhiru Zhang (CoRR, 2025)

Vesper: A Versatile Sparse Linear Algebra Accelerator With Configurable Compute Patterns. - Hanchen Jin; Zichao Yue; Zhongyuan Zhao 004; Yixiao Du; Chenhui Deng; Nitish Srivastava; Zhiru Zhang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)