A 150kHz-BW 15-ENOB Incremental Zoom ADC with Skipped Sampling and Single Buffer Embedded Noise-Shaping SAR Quantizer. - Zongnan Wang; Lu Jie 001; Zichen Kong; Mingtao Zhan; Yi Zhong; Yuan Wang 001; Xiyuan Tang (ISSCC, 2023)

PVTSizing: A TuRBO-RL-Based Batch-Sampling Optimization Framework for PVT-Robust Analog Circuit Synthesis. - Zichen Kong; Xiyuan Tang; Wei Shi 011; Yiheng Du; Yibo Lin; Yuan Wang 001 (DAC, 2024)

LayoutCopilot: An LLM-powered Multi-agent Collaborative Framework for Interactive Analog Layout Design. - Bingyang Liu; Haoyi Zhang; Xiaohan Gao; Zichen Kong; Xiyuan Tang; Yibo Lin; Runsheng Wang; Ru Huang 001 (CoRR, 2024)

LayoutCopilot: An LLM-Powered Multiagent Collaborative Framework for Interactive Analog Layout Design. - Bingyang Liu; Haoyi Zhang; Xiaohan Gao; Zichen Kong; Xiyuan Tang; Yibo Lin; Runsheng Wang; Ru Huang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)