A novel design of leading zero anticipation circuit with parallel error detection. - Ge Zhang 007; Zichu Qi; Weiwu Hu (ISCAS (1), 2005)

Parallel Error Detection for Leading Zero Anticipation. - Ge Zhang 007; Weiwu Hu; Zichu Qi (J. Comput. Sci. Technol., 2006)

Testing content addressable memories using instructions and march-like algorithms. - Lin Ma; Yunji Chen; Menghao Su; Zichu Qi; Heng Zhang; Weiwu Hu (ICECS, 2008)

A Scalable Scan Architecture for Godson-3 Multicore Microprocessor. - Zichu Qi; Hui Liu; Xiangku Li; Da Wang; Yinhe Han 001; Huawei Li 001; Weiwu Hu (Asian Test Symposium, 2009)

A case study of improving at-speed testing coverage of a gigahertz microprocessor. - Zichu Qi; Hui Liu; Xiangku Li; Jun Xu; Weiwu Hu (ICECS, 2009)

Design of Low-Cost High-Performance Floating-Point Fused Multiply-Add with Reduced Power. - Zichu Qi; Qi Guo 001; Ge Zhang 007; Xiangku Li; Weiwu Hu (VLSI Design, 2010)

Godson-3B: A 1GHz 40W 8-core 128GFLOPS processor in 65nm CMOS. - Weiwu Hu; Ru Wang; Yunji Chen; Bao-Xia Fan; Shi-Qiang Zhong; Xiang Gao; Zichu Qi; Xu Yang (ISSCC, 2011)

Design for Testability Features of Godson-3 Multicore Microprocessor. - Zichu Qi; Hui Liu; Xiangku Li; Weiwu Hu (J. Comput. Sci. Technol., 2011)

Godson-3B1500: A 32nm 1.35GHz 40W 172.8GFLOPS 8-core processor. - Weiwu Hu; Yifu Zhang; Liang Yang; Bao-Xia Fan; Yunji Chen; Shi-Qiang Zhong; Huandong Wang; Zichu Qi; Pengyu Wang; Xiang Gao; Xu Yang; Bin Xiao 006; et al. (ISSCC, 2013)

A scan chain optimization method for diagnosis. - Huajun Chen; Zichu Qi; Lin Wang; Chao Xu (ICCD, 2015)