Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation. - Zied Marrakchi; Hayder Mrabet; Habib Mehrez (ReConFig, 2005)

Implementation of Scalable Embedded FPGA for SOC. - Hayder Mrabet; Zied Marrakchi; Habib Mehrez; André Tissot (ReCoSoC, 2005)

A multilevel hierarchical interconnection structure for FPGA. - Hayder Mrabet; Zied Marrakchi; Pierre Souillot; Habib Mehrez (FPGA, 2006)

Configuration tools for a new multilevel hierarchical FPGA. - Zied Marrakchi; Hayder Mrabet; Habib Mehrez (FPGA, 2006)

Performances improvement of FPGA using novel multilevel hierarchical interconnection structure. - Hayder Mrabet; Zied Marrakchi; Pierre Souillot; Habib Mehrez (ICCAD, 2006)

A new Multilevel Hierarchical MFPGA and its suitable configuration tools. - Zied Marrakchi; Hayder Mrabet; Habib Mehrez (ISVLSI, 2006)

Performance Improvement of FPGA Using Novel Multilevel Hierarchical Interconnection Structure. - Hayder Mrabet; Zied Marrakchi; Pierre Souillot; Habib Mehrez; André Tissot (ReCoSoC, 2006)

Efficient Mesh of Tree Interconnect for FPGA Architecture. - Zied Marrakchi; Hayder Mrabet; Christian Masson; Habib Mehrez (FPT, 2007)

Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances. - Zied Marrakchi; Hayder Mrabet; Christian Masson; Habib Mehrez (NOCS, 2007)

A new coarse-grained FPGA architecture exploration environment. - Husain Parvez; Zied Marrakchi; Umer Farooq 001; Habib Mehrez (FPT, 2008)

Efficient tree topology for FPGA interconnect network. - Zied Marrakchi; Hayder Mrabet; Emna Amouri; Habib Mehrez (ACM Great Lakes Symposium on VLSI, 2008)

The Effect of LUT and Cluster Size on a Tree Based FPGA Architecture. - Umer Farooq 001; Zied Marrakchi; Hayder Mrabet; Habib Mehrez (ReConFig, 2008)

Enhanced Methodology and Tools for Exploring Domain-Specific Coarse-Grained FPGAs. - Husain Parvez; Zied Marrakchi; Habib Mehrez (ReConFig, 2008)

Exploration and optimization of tree-based FPGA architectures. (Exploration et optimisation d'architectures FPGA arborescentes). - Zied Marrakchi (2008)

ASIF: Application Specific Inflexible FPGA. - Husain Parvez; Zied Marrakchi; Habib Mehrez (FPT, 2009)

Placement and routing techniques to improve delay balance of WDDL netlist in MFPGA. - Emna Amouri; Hayder Mrabet; Zied Marrakchi; Habib Mehrez (ICECS, 2009)

Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing. - Emna Amouri; Hayder Mrabet; Zied Marrakchi; Habib Mehrez (ReConFig, 2009)

FPGA Interconnect Topologies Exploration. - Zied Marrakchi; Hayder Mrabet; Umer Farooq 001; Habib Mehrez (Int. J. Reconfigurable Comput., 2009)

Controlled placement and routing techniques to improve timing balance of WDDL designs in Mesh-based FPGA. - Emna Amouri; Zied Marrakchi; Habib Mehrez (APCCAS, 2010)

On the optimization of FPGA area depending on target applications. - Zied Marrakchi; Husain Parvez; Alp Kiliç; Habib Mehrez; Hmaied Marrakchi (APCCAS, 2010)

Application Specific FPGA Using Heterogeneous Logic Blocks. - Husain Parvez; Zied Marrakchi; Habib Mehrez (ARC, 2010)

Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only). - Husain Parvez; Zied Marrakchi; Habib Mehrez (FPGA, 2010)

Routability driven placement for mesh-based FPGA architecture. - Mariem Turki; Mohamed Abid; Zied Marrakchi; Habib Mehrez (IDT, 2010)

Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGA. - Umer Farooq 001; Husain Parvez; Zied Marrakchi; Habib Mehrez (ARC, 2011)

Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGA. - Emna Amouri; Zied Marrakchi; Habib Mehrez (ReCoSoC, 2011)

Exploration of Heterogeneous FPGA Architectures. - Umer Farooq 001; Husain Parvez; Habib Mehrez; Zied Marrakchi (Int. J. Reconfigurable Comput., 2011)

Application-Specific FPGA using heterogeneous logic blocks. - Husain Parvez; Zied Marrakchi; Alp Kiliç; Habib Mehrez (ACM Trans. Reconfigurable Technol. Syst., 2011)

A logic sharing synthesis tool for mutually exclusive applications. - Alp Kiliç; Zied Marrakchi; Matthieu Tuna; Habib Mehrez (DTIS, 2012)

Multi-FPGA prototyping environment: Large benchmark generation and signals routing. - Mariem Turki; Habib Mehrez; Zied Marrakchi (ReConFig, 2012)

A new heterogeneous tree-based application specific FPGA and its comparison with mesh-based application specific FPGA. - Umer Farooq 001; Husain Parvez; Habib Mehrez; Zied Marrakchi (Microprocess. Microsystems, 2012)

Designing a 3D tree-based FPGA: Optimization of butterfly programmable interconnect topology using 3D technology. - Vinod Pangracious; Habib Mehrez; Zied Marrakchi (3DIC, 2013)

Data level parallelism for H264/AVC baseline intra-prediction chain on MPSoC. - Nidhameddine Belhadj; Nejmeddine Bahri; Mohamed Ali Ben Ayed; Zied Marrakchi; Habib Mehrez (SSD, 2013)

Performance Analysis and Optimization of High Density Tree-Based 3D Multilevel FPGA. - Vinod Pangracious; Zied Marrakchi; Emna Amouri; Habib Mehrez (ARC, 2013)

Automatic Design Flow for Creating a Custom Multi-FPGA Board Netlist. - Qingshan Tang; Matthieu Tuna; Zied Marrakchi; Habib Mehrez (ARC, 2013)

Iterative Routing Algorithm of Inter-FPGA Signals for Multi-FPGA Prototyping Platform. - Mariem Turki; Zied Marrakchi; Habib Mehrez; Mohamed Abid (ARC, 2013)

Architecture level TSV count minimization methodology for 3D tree-based FPGA. - Vinod Pangracious; Habib Mehrez; Zied Marrakchi (COOL Chips, 2013)

New synthesis approach of hierarchical benchmarks for hardware prototyping. - Mariem Turki; Zied Marrakchi; Mohamed Abid (DTIS, 2013)

High performance 3-dimensional heterogeneous tree-based FPGA architectures (HT-FPGA). - Vinod Pangracious; Habib Mehrez; Umer Farooq 001; Zied Marrakchi (FPGAworld, 2013)

A defect-tolerant cluster in a mesh SRAM-based FPGA. - Arwa Ben Dhia; Saif-Ur Rehman; Adrien Blanchardon; Lirida A. B. Naviner; Mounir Benabdenbi; Roselyne Chotin-Avot; Emna Amouri; Habib Mehrez; Zied Marrakchi (FPT, 2013)

Design and optimization of heterogeneous tree-based FPGA using 3D technology. - Vinod Pangracious; Zied Marrakchi; Habib Mehrez (FPT, 2013)

Physical design exploration of 3D tree-based FPGA architecture. - Vinod Pangracious; Emna Amouri; Habib Mehrez; Zied Marrakchi (ACM Great Lakes Symposium on VLSI, 2013)

TSV count minimization and thermal analysis for 3D Tree-based FPGA. - Vinod Pangracious; Habib Mehrez; Zied Marrakchi (ICICDT, 2013)

Partitioning constraints and signal routing approach for multi-FPGA prototyping platform. - Mariem Turki; Habib Mehrez; Zied Marrakchi; Mohamed Abid (ISSoC, 2013)

Designing 3D tree-based FPGA: Interconnect optimization and thermal analysis. - Vinod Pangracious; Habib Mehrez; Zied Marrakchi (NEWCAS, 2013)

Efficient multilevel interconnect topology for cluster-based mesh FPGA architecture. - Emna Amouri; Adrien Blanchardon; Roselyne Chotin-Avot; Habib Mehrez; Zied Marrakchi (ReConFig, 2013)

Exploration environment for 3D heterogeneous tree-based FPGA architectures (3D HT-FPGA). - Vinod Pangracious; Habib Mehrez; Nizar Beltaief; Zied Marrakchi; Umer Farooq 001 (ReConFig, 2013)

Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA. - Emna Amouri; Habib Mehrez; Zied Marrakchi (Int. J. Reconfigurable Comput., 2013)

Frequency Optimization Objective during System Prototyping on Multi-FPGA Platform. - Mariem Turki; Zied Marrakchi; Habib Mehrez; Mohamed Abid (Int. J. Reconfigurable Comput., 2013)

Exploration and optimization of a homogeneous tree-based application specific inflexible FPGA. - Umer Farooq 001; Husain Parvez; Habib Mehrez; Zied Marrakchi (Microelectron. J., 2013)

Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation. - Sonda Chtourou; Mohamed Abid; Vinod Pangracious; Emna Amouri; Zied Marrakchi; Habib Mehrez (3DIC, 2014)

MPSoC architecture for Component Level Parallelism of H.264/AVC intra prediction encoding chain on SoCLib platform. - Nidhameddine Belhadj; Mohamed Ali Ben Ayed; Nouri Masmoudi; Zied Marrakchi; Habib Mehrez (ATSIP, 2014)

Power consumption analysis for mesh based FPGA. - Sonda Chtourou; Mohamed Abid; Zied Marrakchi; Habib Mehrez (DTIS, 2014)

Exploration and optimization of heterogeneous interconnect fabric of 3D tree-based FPGA. - Vinod Pangracious; Zied Marrakchi; Nizar Beltaief; Habib Mehrez; Umer Farooq 001 (DTIS, 2014)

Towards high performance GHASH for pipelined AES-GCM using FPGAs (abstract only). - Karim M. Abdellatif; Roselyne Chotin-Avot; Zied Marrakchi; Habib Mehrez; Qingshan Tang (FPGA, 2014)

Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA. - Saif-Ur Rehman; Adrien Blanchardon; Arwa Ben Dhia; Mounir Benabdenbi; Roselyne Chotin-Avot; Lirida A. B. Naviner; Lorena Anghel; Habib Mehrez; Emna Amouri; Zied Marrakchi (ISVLSI, 2014)

Flexible reconfigurable architecture for DSP applications. - Abdulfattah Mohammad Obeid; Syed Manzoor Qasim; Mohammed S. BenSaleh; Zied Marrakchi; Habib Mehrez; Heni Ghariani; Mohamed Abid (SoCC, 2014)

On wiring delays reduction of tree-based FPGA using 3-D fabric. - Vinod Pangracious; Mohamed Sahbi Marrakchi; Habib Mehrez; Zied Marrakchi (SoCC, 2014)

MPSoC Architecture for Macro Blocks Line Partitioning of H.264/AVC Encoder. - Nidhameddine Belhadj; Zied Marrakchi; Mohamed Ali Ben Ayed; Nouri Masmoudi; Habib Mehrez (Int. J. Embed. Real Time Commun. Syst., 2014)

A Top-Down Optimization Methodology for Mutually Exclusive Applications. - Alp Kiliç; Zied Marrakchi; Habib Mehrez (Int. J. Reconfigurable Comput., 2014)

Architecture level optimization of 3-dimensional tree-based FPGA. - Vinod Pangracious; Emna Amouri; Zied Marrakchi; Habib Mehrez (Microelectron. J., 2014)

Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization. - Sonda Chtourou; Zied Marrakchi; Vinod Pangracious; Emna Amouri; Habib Mehrez; Mohamed Abid (ARC, 2015)

Signal multiplexing approach to improve inter-FPGA bandwidth of prototyping platform. - Mariem Turki; Zied Marrakchi; Habib Mehrez; Mohamed Abid (Des. Autom. Embed. Syst., 2015)

H.264/AVC high definition intra coding implementation on multiprocessor system on chip technology architecture. - Nidhameddine Belhadj; Nejmeddine Bahri; Zied Marrakchi; Mohamed Ali Ben Ayed; Nouri Masmoudi; Habib Mehrez (IET Comput. Digit. Tech., 2015)

Design and Optimization of a Horizontally Partitioned, High-Speed, 3D Tree-Based FPGA. - Vinod Pangracious; Zied Marrakchi; Habib Mehrez (IEEE Micro, 2015)

Three-Dimensional Design Methodologies for Tree-based FPGA Architecture - Vinod Pangracious; Zied Marrakchi; Habib Mehrez (Springer, 2015)

Rebuilding synthesized design hierarchy based on instances path names of flattened netlist. - Khouloud Bouaziz; Sonda Chtourou; Zied Marrakchi; Abdulfattah Mohammad Obeid; Mohamed Abid (IDT, 2016)

Design of advanced 2D and 3D FPGAs: Architecture-level exploration and algorithm-level optimization. - Sonda Chtourou; Mohamed Abid; Zied Marrakchi; Emna Amouri; Habib Mehrez (IDT, 2016)

Tutorial 2: "Challenges of FPGA-based prototyping & debugging". - Zied Marrakchi; Eman El Mandouh (IDT, 2016)

Embedded FPGA accelerator for Wireless Sensor Network nodes. - Hajer Saidi; Mariem Turki; Zied Marrakchi; Mohammed S. BenSaleh; Mohamed Abid (IDT, 2016)

The effect of interconnect depopulation on FPGA performances in terms of power, area and delay. - Sonda Chtourou; Mohamed Abid; Zied Marrakchi; Emna Amouri; Habib Mehrez (HPCS, 2016)

Exploration of Mesh-Based FPGA Architecture: Comparison of 2D and 3D Technologies in Terms of Power, Area and Performance. - Sonda Chtourou; Zied Marrakchi; Emna Amouri; Vinod Pangracious; Habib Mehrez; Mohamed Abid (PDP, 2016)

Improvement of cluster-based Mesh FPGA architecture using novel hierarchical interconnect topology and long routing wires. - Sonda Chtourou; Zied Marrakchi; Emna Amouri; Vinod Pangracious; Mohamed Abid; Habib Mehrez (Microprocess. Microsystems, 2016)

On Exploiting Partitioning-Based Placement Approach for Performances Improvement of 3D FPGA. - Sonda Chtourou; Mohamed Abid; Zied Marrakchi; Emna Amouri; Habib Mehrez (HPCS, 2017)

Performance analysis and optimization of cluster-based mesh FPGA architectures: design methodology and CAD tool support. - Sonda Chtourou; Zied Marrakchi; Emna Amouri; Vinod Pangracious; Mohamed Abid; Habib Mehrez (Turkish J. Electr. Eng. Comput. Sci., 2017)

Exploration of Clustering Algorithms effects on Mesh of Clusters based FPGA Architecture Performance. - Khouloud Bouaziz; Sonda Chtourou; Zied Marrakchi; Mohamed Abid; Abdulfattah Obeid (HPCS, 2019)

New CAD Tools to ConFigure Tree-Based Embedded FPGA. - Hajer Saidi; Mariem Turki; Zied Marrakchi; M. S. Ben Saleh; Mohamed Abid (HPCS, 2019)

Impact of Clustering Algorithms on the performance of Multilevel Switch Boxes FPGA with Long Wires. - Khouloud Bouaziz; Sonda Chtourou; Mohamed Abid; Zied Marrakchi; Abdulfattah Mohammad Obeid (IWCMC, 2019)

Novel Synthesizable eFPGA based on Island Network with Multilevel Switch Boxes. - Hajer Saidi; Mariem Turki; Zied Marrakchi; Abdulfattah Obeid; Mohamed Abid (AICCSA, 2020)

A-Part: Top-Down Clustering Approach for Mesh of Clusters FPGA. - Khouloud Bouaziz; Sonda Chtourou; Zied Marrakchi; Abdulfattah Mohammad Obeid; Mohamed Abid (ISDA, 2020)

Implementation of Reed Solomon Encoder on Low-Latency Embedded FPGA in Flexible SoC based on ARM Processor. - Hajer Saidi; Mariem Turki; Zied Marrakchi; Abdulfattah Obeid; Mohamed Abid (IWCMC, 2020)

Exploration of Word Width and Cluster Size Effects on Tree-Based Embedded FPGA Using an Automation Framework. - Hajer Saidi; Mariem Turki; Zied Marrakchi; Hela Ben Ahmed; Abdulfattah Obeid; Mohamed Abid (J. Circuits Syst. Comput., 2021)

Mesh of Trees FPGA Architecture: Exploration and Optimization. - Khouloud Bouaziz; Sonda Chtourou; Zied Marrakchi; Abdulfattah Mohammad Obeid; Mohamed Abid (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Development and Analysis of Novel Mesh of Tree-based embedded FPGA. - Hajer Saidi; Mariem Turki; Zied Marrakchi; Mohamed Abid; Abdulfattah Obeid (J. Supercomput., 2022)