Zilin Wang

Orcid: 0009-0005-0281-7879

Affiliations:
  • Peking University, School of Integrated Circuits, Beijing, China


According to our database1, Zilin Wang authored at least 17 papers between 2022 and 2025.

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Bibliography

2025
UniPRE: An SNN-ANN Accelerator With Unified Max-Pooling Prediction and Redundancy Elimination.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2025

PAICORE: A 1.9-Million-Neuron 5.181-TSOPS/W Digital Neuromorphic Processor With Unified SNN-ANN and On-Chip Learning Paradigm.
IEEE J. Solid State Circuits, February, 2025

HyNITA: A Neuromorphic Inference and Training Accelerator for Hybrid ANN-SNN Fusion Models.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

CROSSCUT: A Multi-Core Neuromorphic Accelerator Improving Resource-Utilization.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025

NeuroHexa: A 2D/3D-Scalable Model-Adaptive NoC Architecture for Neuromorphic Computing.
Proceedings of the Design, Automation & Test in Europe Conference, 2025

2024
Marmotini: A Weight Density Adaptation Architecture With Hybrid Compression Method for Spiking Neural Network.
IEEE Trans. Very Large Scale Integr. Syst., December, 2024

NeuroREC: A 28-nm Efficient Neuromorphic Processor for Radar Emitter Classification.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2024

BrainQN: Enhancing the Robustness of Deep Reinforcement Learning with Spiking Neural Networks.
Adv. Intell. Syst., September, 2024

An Efficient Spiking Convolutional Architecture with Compressed Address Event Representation and Adaptive Delay Asynchronous Clocks.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2024

A Hybrid Heterogeneous Neural Network Accelerator based on Systolic Array.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

On-Chip Incremental Learning based on Unsupervised STDP Implementation.
Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2023
An Efficient Neuromorphic Implementation of Temporal Coding-Based On-Chip STDP Learning.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2023

A Spiking Neural Network Accelerator based on Ping-Pong Architecture with Sparse Spike and Weight.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

An Efficient Spiking Neural Network Accelerator with Sparse Weight.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2023

Unsupervised Learning of Spike-Timing-Dependent Plasticity Based on a Neuromorphic Implementation.
Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022
ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator.
IEEE Trans. Very Large Scale Integr. Syst., 2022

An Event-driven Spiking Neural Network Accelerator with On-chip Sparse Weight.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022


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