An Event-driven Spiking Neural Network Accelerator with On-chip Sparse Weight. - Yisong Kuang; Xiaoxin Cui; Chenglong Zou; Yi Zhong; Zhenhui Dai; Zilin Wang 001; Kefei Liu 002; Dunshan Yu; Yuan Wang 001 (ISCAS, 2022)

ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator. - Yisong Kuang; Xiaoxin Cui; Zilin Wang 001; Chenglong Zou; Yi Zhong; Kefei Liu 002; Zhenhui Dai; Dunshan Yu; Yuan Wang 001; Ru Huang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Unsupervised Learning of Spike-Timing-Dependent Plasticity Based on a Neuromorphic Implementation. - Yi Zhong; Zilin Wang 001; Xiaoxin Cui; Jian Cao 002; Yuan Wang 001 (AICAS, 2023)

An Efficient Spiking Neural Network Accelerator with Sparse Weight. - Zilin Wang 001; Yi Zhong; Youming Yang 002; Xiaoxin Cui; Yuan Wang 001 (BioCAS, 2023)

A Spiking Neural Network Accelerator based on Ping-Pong Architecture with Sparse Spike and Weight. - Zilin Wang 001; Yi Zhong; Xiaoxin Cui; Yisong Kuang; Yuan Wang 001 (ISCAS, 2023)

An Efficient Neuromorphic Implementation of Temporal Coding-Based On-Chip STDP Learning. - Yi Zhong; Zilin Wang 001; Xiaoxin Cui; Jian Cao 002; Yuan Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

On-Chip Incremental Learning based on Unsupervised STDP Implementation. - Guang Chen; Jian Cao 002; Shuo Feng; Zilin Wang 001; Yi Zhong; Qibin Li; Xiongbo Zhao; Xing Zhang 002; Yuan Wang 001 (AICAS, 2024)

A Hybrid Heterogeneous Neural Network Accelerator based on Systolic Array. - Zilin Wang 001; Yi Zhong; Guang Chen; Shuo Feng; Youming Yang 002; Xiaoxin Cui; Yuan Wang 001 (AICAS, 2024)

An Efficient Spiking Convolutional Architecture with Compressed Address Event Representation and Adaptive Delay Asynchronous Clocks. - Zhenhui Dai; Li Lun; Zilin Wang 001; Jiawei Wang; Kunyu Feng; Yuan Wang 001; Dunshan Yu; Xiaoxin Cui (BioCAS, 2024)

BrainQN: Enhancing the Robustness of Deep Reinforcement Learning with Spiking Neural Networks. - Shuo Feng; Jian Cao 002; Zehong Ou; Guang Chen; Yi Zhong; Zilin Wang 001; Juntong Yan; Jue Chen; Bingsen Wang; Chenglong Zou; Zebang Feng; Yuan Wang 001 (Adv. Intell. Syst., 2024)

NeuroREC: A 28-nm Efficient Neuromorphic Processor for Radar Emitter Classification. - Zilin Wang 001; Zehong Ou; Yi Zhong; Youming Yang 002; Li Lun; Hufei Li; Jian Cao 002; Xiaoxin Cui; Song Jia; Yuan Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Marmotini: A Weight Density Adaptation Architecture With Hybrid Compression Method for Spiking Neural Network. - Zilin Wang 001; Yi Zhong; Zehong Ou; Youming Yang 002; Shuo Feng; Guang Chen; Xiaoxin Cui; Song Jia; Yuan Wang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2024)

NeuroHexa: A 2D/3D-Scalable Model-Adaptive NoC Architecture for Neuromorphic Computing. - Yi Zhong; Zilin Wang 001; Yipeng Gao; Xiaoxin Cui; Xing Zhang 002; Yuan Wang 001 (DATE, 2025)

CROSSCUT: A Multi-Core Neuromorphic Accelerator Improving Resource-Utilization. - Youming Yang 002; Yi Zhong; Zilin Wang 001; Tao Zhang 140; Li Lun; Yingying Cui; Xiaoxin Cui; Song Jia; Yuan Wang 001 (ISCAS, 2025)

HyNITA: A Neuromorphic Inference and Training Accelerator for Hybrid ANN-SNN Fusion Models. - Yi Zhong; Li Lun; Zilin Wang 001; Jinhao Ruan; Yipeng Gao; Xiaoxin Cui; Xing Zhang 002; Yuan Wang 001 (ISCAS, 2025)

PAICORE: A 1.9-Million-Neuron 5.181-TSOPS/W Digital Neuromorphic Processor With Unified SNN-ANN and On-Chip Learning Paradigm. - Yi Zhong; Yisong Kuang; Kefei Liu 002; Zilin Wang 001; Shuo Feng; Guang Chen; Youming Yang 002; Xiuping Cui; Qiankun Wang; Jian Cao 002; Song Jia; Yun Liang 001; et al. (IEEE J. Solid State Circuits, 2025)

UniPRE: An SNN-ANN Accelerator With Unified Max-Pooling Prediction and Redundancy Elimination. - Tao Zhang 140; Yi Zhong; Youming Yang 002; Zilin Wang 001; Zhaotong Zhang; Yuan Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)