A Nonlinearity-Calibration-Free Reconfigurable ADPLL for General Purpose Frequency Modulation. - Zixiang Wan; Woogeun Rhee; Zhihua Wang 001 (ICTA, 2020)

A 0.0048mm2 0.43-to-1.0V 0.54-to-1.76GHz Bias-Current-Free PLL in 14nm FinFET CMOS. - Zixiang Wan; Xinyu Xu; Woogeun Rhee; Zhihua Wang 001 (ICTA, 2021)

Design and Analysis of DTC-Free ΔΣ Bang-Bang Phase-Locked Loops. - Zixiang Wan; Woogeun Rhee; Zhihua Wang 001 (ISCAS, 2021)

A Bias-Current-Free Fractional-N Hybrid PLL for Low-Voltage Clock Generation. - Xinyu Xu; Zixiang Wan; Woogeun Rhee; Zhihua Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Metadata-Enhanced Speech Emotion Recognition: Augmented Residual Integration and Co-Attention in Two-Stage Fine-Tuning. - Zixiang Wan; Ziyue Qiu; Yiyang Liu; Wei-Qiang Zhang (ICASSP, 2025)