A timing failure tolerance design with in-field simultaneous error detection and correction. - Ziyi Hao; Xiaoyan Xiang; Chen Chen 058; Jianyi Meng (ASICON, 2015)

EDSU: Error detection and sampling unified flip-flop with ultra-low overhead. - Ziyi Hao; Xiaoyan Xiang; Chen Chen 058; Jianyi Meng; Yong Ding 003; Xiaolang Yan (IEICE Electron. Express, 2016)

Xuantie-910: Innovating Cloud and Edge Computing by RISC-V. - Chen Chen 058; Xiaoyan Xiang; Chang Liu 021; Yunhai Shang; Ren Guo; Dongqi Liu 003; Yimin Lu; Ziyi Hao; Jiahui Luo; Zhijian Chen; Chunqiang Li; Yu Pu; et al. (Hot Chips Symposium, 2020)

Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product. - Chen Chen 058; Xiaoyan Xiang; Chang Liu 021; Yunhai Shang; Ren Guo; Dongqi Liu 003; Yimin Lu; Ziyi Hao; Jiahui Luo; Zhijian Chen; Chunqiang Li; Yu Pu; et al. (ISCA, 2020)