Graph Learning-Based Arithmetic Block Identification. - Zhuolun He; Ziyi Wang 010; Chen Bai; Haoyu Yang; Bei Yu 001 (ICCAD, 2021)

Functionality matters in netlist representation learning. - Ziyi Wang 010; Chen Bai; Zhuolun He; Guangliang Zhang; Qiang Xu 001; Tsung-Yi Ho; Bei Yu 001; Yu Huang 005 (DAC, 2022)

Concurrent Sign-off Timing Optimization via Deep Steiner Points Refinement. - Siting Liu 002; Ziyi Wang 010; Fangzhou Liu; Yibo Lin; Bei Yu 001; Martin D. F. Wong (DAC, 2023)

Restructure-Tolerant Timing Prediction via Multimodal Fusion. - Ziyi Wang 010; Siting Liu 002; Yuan Pu 001; Song Chen 001; Tsung-Yi Ho; Bei Yu 001 (DAC, 2023)

Efficient Arithmetic Block Identification With Graph Learning and Network-Flow. - Ziyi Wang 010; Zhuolun He; Chen Bai; Haoyu Yang; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Disentangle, Align and Generalize: Learning A Timing Predictor from Different Technology Nodes. - Xinyun Zhang; Binwu Zhu; Fangzhou Liu; Ziyi Wang 010; Peng Xu; Hong Xu 001; Bei Yu 001 (DAC, 2024)

Routing-aware Legal Hybrid Bonding Terminal Assignment for 3D Face-to-Face Stacked ICs. - Siting Liu 002; Jiaxi Jiang; Zhuolun He; Ziyi Wang 010; Yibo Lin; Bei Yu 001; Martin D. F. Wong (ISPD, 2024)

Large circuit models: opportunities and challenges. - Lei Chen; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Ru Huang 001; Yu Huang 005; Sadaf Khan; Min Li; Xingquan Li; Yu Li; Yun Liang 001; et al. (Sci. China Inf. Sci., 2024)

Erratum to: Large circuit models: opportunities and challenges. - Lei Chen; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Ru Huang 001; Yu Huang 005; Sadaf Khan; Min Li; Xingquan Li; Yu Li; Yun Liang 001; et al. (Sci. China Inf. Sci., 2024)

The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models. - Lei Chen 002; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Yu Huang 005; Sadaf Khan; Min Li 019; Xingquan Li; Yun Liang 001; Yibo Lin; Jinwei Liu; et al. (CoRR, 2024)

HeLO: A Heterogeneous Logic Optimization Framework by Hierarchical Clustering and Graph Learning. - Yuan Pu 001; Fangzhou Liu; Zhuolun He; Keren Zhu 001; Rongliang Fu; Ziyi Wang 010; Tsung-Yi Ho; Bei Yu 001 (ISPD, 2025)

GraphCAD: Leveraging Graph Neural Networks for Accuracy Prediction Handling Crosstalk-affected Delays. - Fangzhou Liu; Guannan Guo; Yuyang Ye 001; Ziyi Wang 010; Wenjie Fu 003; Weihua Sheng; Bei Yu 001 (ISPD, 2025)

FGNN2: A Powerful Pretraining Framework for Learning the Logic Functionality of Circuits. - Ziyi Wang 010; Chen Bai; Zhuolun He; Guangliang Zhang; Qiang Xu 001; Tsung-Yi Ho; Yu Huang 005; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Self-Supervised Graph Contrastive Pretraining for Device-level Integrated Circuits. - Sungyoung Lee 004; Ziyi Wang 010; Seunggeun Kim; Taekyun Lee; David Z. Pan (CoRR, 2025)

ParSGCN: Bridging the Gap Between Emulation Partitioning and Scheduling. - Ziyi Wang 010; Wenqian Zhao; Yuan Pu 001; Lei Chen 031; Wilson W. K. Thong; Weihua Sheng; Tsung-Yi Ho; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Sign-Off Timing Considerations via Concurrent Routing Topology Optimization. - Siting Liu 002; Ziyi Wang 010; Fangzhou Liu; Yibo Lin; Bei Yu 001; Martin D. F. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Prerouting Timing Prediction Across Different Technology Nodes. - Xinyun Zhang; Binwu Zhu; Fangzhou Liu; Jiaxi Jiang; Ziyi Wang 010; Peng Xu; Hong Xu 001; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)