A Dual-Slope Capacitance-to-Digital Converter Integrated in an Implantable Pressure-Sensing System. - Sechang Oh 001; Yoonmyung Lee; Jingcheng Wang; Zhiyoong Foo; Yejoong Kim; Wanyeong Jung; Ziyun Li 001; David T. Blaauw; Dennis Sylvester (IEEE J. Solid State Circuits, 2015)

Low complexity optical flow using neighbor-guided semi-global matching. - Jiang Xiang; Ziyun Li 001; David T. Blaauw; Hun-Seok Kim; Chaitali Chakrabarti (ICIP, 2016)

26.7 A 10mm3 syringe-implantable near-field radio system on glass substrate. - Yao Shi 001; Myungjoon Choi; Ziyun Li 001; Gyouho Kim; Zhiyoong Foo; Hun-Seok Kim; David D. Wentzloff; David T. Blaauw (ISSCC, 2016)

A 10 mm3 Inductive Coupling Radio for Syringe-Implantable Smart Sensor Nodes. - Yao Shi 001; Myungjoon Choi; Ziyun Li 001; Zhihong Luo; Gyouho Kim; Zhiyoong Foo; Hun-Seok Kim; David D. Wentzloff; David T. Blaauw (IEEE J. Solid State Circuits, 2016)

14.7 A 288µW programmable deep-learning processor with 270KB on-chip weight storage using non-uniform memory hierarchy for mobile intelligence. - Suyoung Bang; Jingcheng Wang; Ziyun Li 001; Cao Gao; Yejoong Kim; Qing Dong 001; Yen-Po Chen; Laura Fick; Xun Sun; Ronald G. Dreslinski; Trevor N. Mudge; Hun-Seok Kim; et al. (ISSCC, 2017)

11.2 A 1Mb embedded NOR flash memory with 39µW program power for mm-scale high-temperature sensor nodes. - Qing Dong 001; Yejoong Kim; Inhee Lee 001; Myungjoon Choi; Ziyun Li 001; Jingcheng Wang; Kaiyuan Yang 001; Yen-Po Chen; Junjie Dong; Minchang Cho; Gyouho Kim; Wei-Keng Chang; et al. (ISSCC, 2017)

3.7 A 1920×1080 30fps 2.3TOPS/W stereo-depth processor for robust autonomous navigation. - Ziyun Li 001; Qing Dong 001; Mehdi Saligane; Benjamin P. Kempke; Shijia Yang; Zhengya Zhang; Ronald G. Dreslinski; Dennis Sylvester; David T. Blaauw; Hun-Seok Kim (ISSCC, 2017)

A1920 × 1080 25FPS, 2.4TOPS/W Unified Optical Flow and Depth 6D Vision Processor for Energy-Efficient, Low Power Autonomous Navigation. - Ziyun Li 001; Jingcheng Wang; Dennis Sylvester; David T. Blaauw; Hun-Seok Kim (VLSI Circuits, 2018)

A 1920 × 1080 30-frames/s 2.3 TOPS/W Stereo-Depth Processor for Energy-Efficient Autonomous Navigation of Micro Aerial Vehicles. - Ziyun Li 001; Qing Dong 001; Mehdi Saligane; Benjamin P. Kempke; Luyao Gong; Zhengya Zhang; Ronald G. Dreslinski; Dennis Sylvester; David T. Blaauw; Hun-Seok Kim (IEEE J. Solid State Circuits, 2018)

An 879GOPS 243mW 80fps VGA Fully Visual CNN-SLAM Processor for Wide-Range Autonomous Exploration. - Ziyun Li 001; Yu Chen 070; Luyao Gong; Lu Liu; Dennis Sylvester; David T. Blaauw; Hun-Seok Kim (ISSCC, 2019)

A 1920 $ times$ 1080 25-Frames/s 2.4-TOPS/W Low-Power 6-D Vision Processor for Unified Optical Flow and Stereo Depth With Semi-Global Matching. - Ziyun Li 001; Jingcheng Wang; Dennis Sylvester; David T. Blaauw; Hun-Seok Kim (IEEE J. Solid State Circuits, 2019)

Low Complexity, Hardware-Efficient Neighbor-Guided SGM Optical Flow for Low-Power Mobile Vision Applications. - Ziyun Li 001; Jiang Xiang; Luyao Gong; David T. Blaauw; Chaitali Chakrabarti; Hun-Seok Kim (IEEE Trans. Circuits Syst. Video Technol., 2019)

AA-ResNet: Energy Efficient All-Analog ResNet Accelerator. - Jongyup Lim; Myungjoon Choi; Bowen Liu 001; Taewook Kang; Ziyun Li 001; Zhehong Wang; Yiqun Zhang 002; Kaiyuan Yang 001; David T. Blaauw; Hun-Seok Kim; Dennis Sylvester (MWSCAS, 2020)

A 170μW Image Signal Processor Enabling Hierarchical Image Recognition for Intelligence at the Edge. - Hyochan An; Siddharth Venkatesan; Sam Schiferl; Tim Wesley; Qirui Zhang 001; Jingcheng Wang; Kyojin Choo; Shiyu Liu; Bowen Liu 001; Ziyun Li 001; Hengfei Zhong; Luyao Gong; et al. (VLSI Circuits, 2020)

An All-Weights-on-Chip DNN Accelerator in 22nm ULL Featuring 24×1 Mb eRRAM. - Zhehong Wang; Ziyun Li 001; Li Xu 006; Qing Dong 001; Chin-I Su; Wen-Ting Chu; George Tsou; Yu-Der Chih; Tsung-Yung Jonathan Chang; Dennis Sylvester; Hun-Seok Kim; David T. Blaauw (VLSI Circuits, 2020)

An Ultra-Low-Power Image Signal Processor for Hierarchical Image Recognition With Deep Neural Networks. - Hyochan An; Sam Schiferl; Siddharth Venkatesan; Tim Wesley; Qirui Zhang 001; Jingcheng Wang; Kyojin Choo; Shiyu Liu; Bowen Liu 001; Ziyun Li 001; Luyao Gong; Hengfei Zhong; et al. (IEEE J. Solid State Circuits, 2021)

RRAM-DNN: An RRAM and Model-Compression Empowered All-Weights-On-Chip DNN Accelerator. - Ziyun Li 001; Zhehong Wang; Li Xu 006; Qing Dong 001; Bowen Liu 001; Chin-I Su; Wen-Ting Chu; George Tsou; Yu-Der Chih; Tsung-Yung Jonathan Chang; Dennis Sylvester; Hun-Seok Kim; et al. (IEEE J. Solid State Circuits, 2021)

EyeCoD: eye tracking system acceleration via flatcam-based algorithm & accelerator co-design. - Haoran You; Cheng Wan 005; Yang Zhao 013; Zhongzhi Yu; Yonggan Fu; Jiayi Yuan 001; Shang Wu 003; Shunyao Zhang; Yongan Zhang; Chaojian Li; Vivek Boominathan; Ashok Veeraraghavan; et al. (ISCA, 2022)

A 22nm 3.5TOPS/W Flexible Micro-Robotic Vision SoC with 2MB eMRAM for Fully-on-Chip Intelligence. - Qirui Zhang 001; Hyochan An; Zichen Fan; Zhehong Wang; Ziyun Li 001; Guanru Wang; Hun-Seok Kim; David T. Blaauw; Dennis Sylvester (VLSI Technology and Circuits, 2022)

i-FlatCam: A 253 FPS, 91.49 µJ/Frame Ultra-Compact Intelligent Lensless Camera for Real-Time and Efficient Eye Tracking in VR/AR. - Yang Zhao 013; Ziyun Li 001; Yonggan Fu; Yongan Zhang; Chaojian Li; Cheng Wan 005; Haoran You; Shang Wu 003; Xu Ouyang; Vivek Boominathan; Ashok Veeraraghavan; Yingyan Lin 001 (VLSI Technology and Circuits, 2022)

Distributed On-Sensor Compute System for AR/VR Devices: A Semi-Analytical Simulation Framework for Power Estimation. - Jorge Gomez 001; Saavan Patel; Syed Shakib Sarwar; Ziyun Li 001; Raffaele Capoccia; Zhao Wang; Reid Pinkham; Andrew Berkovich; Tsung-Hsun Tsai; Barbara De Salvo; Chiao Liu (CoRR, 2022)

Memory-Oriented Design-Space Exploration of Edge-AI Hardware for XR Applications. - Vivek Parmar; Syed Shakib Sarwar; Ziyun Li 001; Hsien-Hsin S. Lee; Barbara De Salvo; Manan Suri (CoRR, 2022)

Fully-Binarized Distance Computation based On-device Few-Shot Learning for XR applications. - Vivek Parmar; Sandeep Kaur Kingra; Syed Shakib Sarwar; Ziyun Li 001; Barbara De Salvo; Manan Suri (CVPR Workshops, 2023)

Siracusa: A Low-Power On-Sensor RISC-V SoC for Extended Reality Visual Processing in 16nm CMOS. - Moritz Scherer 001; Manuel Eggimann; Alfio Di Mauro; Arpan Suravi Prasad; Francesco Conti 001; Davide Rossi 001; Jorge Tomás Gómez; Ziyun Li 001; Syed Shakib Sarwar; Zhao Wang; Barbara De Salvo; Luca Benini (ESSCIRC, 2023)

Exploring Memory-Oriented Design Optimization of Edge AI Hardware for Extended Reality Applications. - Vivek Parmar; Syed Shakib Sarwar; Ziyun Li 001; Hsien-Hsin S. Lee; Barbara De Salvo; Manan Suri (IEEE Micro, 2023)

EyeCoD: Eye Tracking System Acceleration via FlatCam-Based Algorithm and Hardware Co-Design. - Haoran You; Yang Zhao 013; Cheng Wan 005; Zhongzhi Yu; Yonggan Fu; Jiayi Yuan 001; Shang Wu 003; Shunyao Zhang; Yongan Zhang; Chaojian Li; Vivek Boominathan; Ashok Veeraraghavan; et al. (IEEE Micro, 2023)

Neural Architecture Search of Hybrid Models for NPU-CIM Heterogeneous AR/VR Devices. - Yiwei Zhao; Ziyun Li 001; Win-San Khwa; Xiaoyu Sun 001; Sai Qian Zhang; Syed Shakib Sarwar; Kleber Hugo Stangherlin; Yi-Lun Lu; Jorge Tomás Gómez; Jae-Sun Seo; Phillip B. Gibbons; Barbara De Salvo; et al. (CoRR, 2024)

Estimating Power, Performance, and Area for On-Sensor Deployment of AR/VR Workloads Using an Analytical Framework. - Xiaoyu Sun 001; Xiaochen Peng; Sai Qian Zhang; Jorge Gomez 002; Win-San Khwa; Syed Shakib Sarwar; Ziyun Li 001; Weidong Cao 001; Zhao Wang; Chiao Liu; Meng-Fan Chang; Barbara De Salvo; et al. (ACM Trans. Design Autom. Electr. Syst., 2024)

Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neural Engine. - Arpan Suravi Prasad; Moritz Scherer 001; Francesco Conti 001; Davide Rossi 001; Alfio Di Mauro; Manuel Eggimann; Jorge Tomás Gómez; Ziyun Li 001; Syed Shakib Sarwar; Zhao Wang; Barbara De Salvo; Luca Benini (IEEE J. Solid State Circuits, 2024)

RoboVisio: A Micro-Robot Vision Domain-Specific SoC for Autonomous Navigation Enabling Fully-on-Chip Intelligence via 2-MB eMRAM. - Qirui Zhang 001; Zichen Fan; Hyochan An; Zhehong Wang; Ziyun Li 001; Guanru Wang; Pierre Abillama; Hun-Seok Kim; David T. Blaauw; Dennis Sylvester (IEEE J. Solid State Circuits, 2024)

Thermally Constrained Codesign of Heterogeneous 3-D Integration of Compute-in-Memory, Digital ML Accelerator, and RISC-V Cores for Mixed ML and Non-ML Workloads. - Yuan-Chun Luo; Anni Lu; Janak Sharda; Moritz Scherer 001; Jorge Tomás Gómez; Syed Shakib Sarwar; Ziyun Li 001; Reid Frederick Pinkham; Barbara De Salvo; Shimeng Yu (IEEE Trans. Very Large Scale Integr. Syst., 2024)

H4H: Hybrid Convolution-Transformer Architecture Search for NPU-CIM Heterogeneous Systems for AR/VR Applications. - Yiwei Zhao; Jinhui Chen; Sai Qian Zhang; Syed Shakib Sarwar; Kleber Hugo Stangherlin; Jorge Tomás Gómez; Jae-Sun Seo; Barbara De Salvo; Chiao Liu; Phillip B. Gibbons; Ziyun Li 001 (ASP-DAC, 2025)

H4H: Hybrid Convolution-Transformer Architecture Search for NPU-CIM Heterogeneous Systems for AR/VR Applications (Abstract). - Yiwei Zhao; Jinhui Chen; Sai Qian Zhang; Syed Shakib Sarwar; Kleber Hugo Stangherlin; Jorge Tomás Gómez; Jae-Sun Seo; Barbara De Salvo; Chiao Liu; Phillip B. Gibbons; Ziyun Li 001 (HOPC@SPAA, 2025)

AdaVFM: Adaptive Vision Foundation Models for Edge Intelligence via LLM-Guided Execution. - Yiwei Zhao; Yi Zheng; Huapeng Su; Jieyu Lin; Stefano Ambrogio; Cijo Jose; Michaël Ramamonjisoa; Patrick Labatut; Barbara De Salvo; Chiao Liu; Phillip B. Gibbons; Ziyun Li 001 (CoRR, 2026)