Teaching Platform for Network Communication and Protocols Using a Micro: bit Based Wheeled Robot. - Zizhang Luo; Yuxuan Zhou; Bohan Yu; Junfeng Hu (SIGCSE, 2020)

TensorLib: A Spatial Accelerator Generation Framework for Tensor Algebra. - Liancheng Jia; Zizhang Luo; Liqiang Lu; Yun Liang 001 (DAC, 2021)

TENET: A Framework for Modeling Tensor Dataflow Based on Relation-centric Notation. - Liqiang Lu; Naiqing Guan; Yuyue Wang 001; Liancheng Jia; Zizhang Luo; Jieming Yin; Jason Cong; Yun Liang 001 (ISCA, 2021)

Analyzing the Design Space of Spatial Tensor Accelerators on FPGAs. - Liancheng Jia; Zizhang Luo; Liqiang Lu; Yun Liang 001 (ISVLSI, 2021)

Sanger: A Co-Design Framework for Enabling Sparse Attention using Reconfigurable Architecture. - Liqiang Lu; Yicheng Jin; Hangrui Bi; Zizhang Luo; Peng Li 031; Tao Wang 004; Yun Liang 001 (MICRO, 2021)

Rubick: A Synthesis Framework for Spatial Architectures via Dataflow Decomposition. - Zizhang Luo; Liqiang Lu; Size Zheng 001; Jieming Yin; Jason Cong; Jianwei Yin; Yun Liang 001 (DAC, 2023)

Calabash: Accelerating Attention Using a Systolic Array Chain on FPGAs. - Zizhang Luo; Liqiang Lu; Yicheng Jin; Liancheng Jia; Yun Liang 001 (FPL, 2023)

Automatic Generation of Spatial Accelerator for Tensor Algebra. - Liancheng Jia; Zizhang Luo; Liqiang Lu; Yun Liang 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Cement: Streamlining FPGA Hardware Design with Cycle-Deterministic eHDL and Synthesis. - Youwei Xiao; Zizhang Luo; Kexing Zhou; Yun Liang 001 (FPGA, 2024)

Rubick: A Unified Infrastructure for Analyzing, Exploring, and Implementing Spatial Architectures via Dataflow Decomposition. - Liqiang Lu; Zizhang Luo; Size Zheng 001; Jieming Yin; Jason Cong; Yun Liang 001; Jianwei Yin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)