MUG5: Modeling of Universal Chiplet Interconnect Express (UCIe) Standard Based on gem5. - Xiaoyan Li; Zizheng Dong; Shuaipeng Li; Sai Gao; Jianfei Jiang 001; Guanghui He; Zhigang Mao (ASICON, 2023)

A $ boldsymbol{4} times boldsymbol{112}- mathbf{Gb}/ mathbf{s}$ PAM-4 Silicon-Photonic Transceiver Front-End for Linear-Drive Co-Packaged Optics. - Han Liu; Nan Qi; Donglai Lu; Zizheng Dong; Zhihan Zhang; Jian He; Guike Li; Leliang Li; Ye Liu; Ziyue Dang; Daigao Chen; Zhao Zhang 004; et al. (A-SSCC, 2023)

A 0.8-ps RMS Precision Period Jitter Measurement Circuit with Offset Reduction. - Lin Xie; Zizheng Dong; Jialei Sun; Sai Gao; Shuaipeng Li; Naifeng Jing; Qin Wang 009; Jianfei Jiang 001 (ISCAS, 2024)

A Hierarchical 3-D Physical Design Method for Ultralarge-Scale Logic-on-Memory CGRA Chip. - Zizheng Dong; Shuaipeng Li; Weijia Zhu; Ang Li; Qin Wang 009; Naifeng Jing; Weiguang Sheng; Jianfei Jiang 001; Zhigang Mao (IEEE Trans. Very Large Scale Integr. Syst., 2025)

An Energy-Efficient CPU-FPGA Heterogeneous Acceleration System for Third-Generation Genomic Sequencing Based on Minimap2. - Jialei Sun; Lingyi Liu; Kunyue Li; Shuaipeng Li; Sai Gao; Zizheng Dong; Jianfei Jiang 001; Fangzhen Wu (IEEE Trans. Circuits Syst. II Express Briefs, 2025)