Utilizing Various ADL Facets for Instruction Level CPU Test. - Elham Safi; Zohreh Karimi; Maghsoud Abbaspour; Zainalabedin Navabi (MTV, 2003)

Processor Testing Using an ADL Description and Genetic Algorithms. - Elham Safi; Reihaneh Saberi; Zohreh Karimi; Zainalabedin Navabi (VLSI-SOC, 2003)

Block placement to ensure channel routability. - Shigetoshi Nakatake; Zohreh Karimi; Taraneh Taghavi; Majid Sarrafzadeh (ACM Great Lakes Symposium on VLSI, 2007)

Power aware placement for FPGAs with dual supply voltages. - Zohreh Karimi; Majid Sarrafzadeh (ISQED, 2009)

Fine-grained post placement voltage assignment considering level shifter overhead. - Zohreh Karimi; Majid Sarrafzadeh (VLSI-SoC, 2010)