Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors. - Anupam Chattopadhyay; Zoltan Endre Rakosi; Kingshuk Karuri; David Kammler; Rainer Leupers; Gerd Ascheid; Heinrich Meyr (IEEE International Workshop on Rapid System Prototyping, 2007)

Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors. - Anupam Chattopadhyay; Harold Ishebabi; Xiaolin Chen; Zoltan Endre Rakosi; Kingshuk Karuri; David Kammler; Rainer Leupers; Gerd Ascheid; Heinrich Meyr (ACM Trans. Embed. Comput. Syst., 2008)

Hot-Swapping architecture extension for mitigation of permanent functional unit faults. - Zoltan Endre Rakosi; Masayuki Hiromoto; Hiroyuki Ochi; Yukihiro Nakamura (FPL, 2009)

Adaptive Energy-Efficient Architecture for WCDMA Channel Estimation. - Zoltan Endre Rakosi; Zheng Wang 020; Anupam Chattopadhyay (ReConFig, 2011)

Combinational logic synthesis for material implication. - Anupam Chattopadhyay; Zoltan Endre Rakosi (VLSI-SoC, 2011)

Design and analysis of layered coarse-grained reconfigurable architecture. - Zoltán Endre Rákossy; Tejas Naphade; Anupam Chattopadhyay (ReConFig, 2012)

ASIC synthesis using Architecture Description Language. - Zheng Wang 020; Xiao Wang; Anupam Chattopadhyay; Zoltan Endre Rakosi (VLSI-DAT, 2012)

High-Level Design Space and Flexibility Exploration for Adaptive, Energy-Efficient WCDMA Channel Estimation Architectures. - Zoltán Endre Rákossy; Zheng Wang 020; Anupam Chattopadhyay (Int. J. Reconfigurable Comput., 2012)

CoARX: a coprocessor for ARX-based cryptographic algorithms. - Khawar Shahzad; Ayesha Khalid; Zoltán Endre Rákossy; Goutam Paul 001; Anupam Chattopadhyay (DAC, 2013)

Hot-swapping architecture with back-biased testing for mitigation of permanent faults in functional unit array. - Zoltán Endre Rákossy; Masayuki Hiromoto; Hiroshi Tsutsui; Takashi Sato 001; Yukihiro Nakamura; Hiroyuki Ochi (DATE, 2013)

Exploiting architecture description language for diverse IP synthesis in heterogeneous MPSoC. - Zoltán Endre Rákossy; Axel Acosta-Aponte; Anupam Chattopadhyay (ReConFig, 2013)

Efficient and scalable CGRA-based implementation of Column-wise Givens Rotation. - Zoltán Endre Rákossy; Farhad Merchant; Axel Acosta-Aponte; S. K. Nandy 001; Anupam Chattopadhyay (ASAP, 2014)

Force-directed scheduling for Data Flow Graph mapping on Coarse-Grained Reconfigurable Architectures. - Alexander Fell; Zoltán Endre Rákossy; Anupam Chattopadhyay (ReConFig, 2014)

Modeling, analysis and exploration of layers: A 3D computing architecture. - Zoltán Endre Rákossy (VLSI-SoC, 2014)

Scalable and energy-efficient reconfigurable accelerator for column-wise givens rotation. - Zoltán Endre Rákossy; Farhad Merchant; Axel Acosta-Aponte; S. K. Nandy 001; Anupam Chattopadhyay (VLSI-SoC, 2014)

Scalable and Efficient Linear Algebra Kernel Mapping for Low Energy Consumption on the Layers CGRA. - Zoltán Endre Rákossy; Dominik Stengele; Axel Acosta-Aponte; Saumitra Chafekar; Paolo Bientinesi; Anupam Chattopadhyay (ARC, 2015)

Design and synthesis of reconfigurable control-flow structures for CGRA. - Zoltán Endre Rákossy; Axel Acosta-Aponte; Tobias G. Noll; Gerd Ascheid; Rainer Leupers; Anupam Chattopadhyay (ReConFig, 2015)

Exploiting scalable CGRA mapping of LU for energy efficiency using the Layers architecture. - Zoltán Endre Rákossy; Dominik Stengele; Gerd Ascheid; Rainer Leupers; Anupam Chattopadhyay (VLSI-SoC, 2015)