A high efficiency all-PMOS charge pump for 3D NAND flash memory. - Liyin Fu; Yu Wang 097; Qi Wang 041; Shiyang Yang; Yan Yang; Zongliang Huo (ASICON, 2015)

A novel adaptive CMOS low-dropout regulator with 3A sink/source capability. - Yan Yang; Qi Wang 041; Yu Wang 097; Liyin Fu; Zongliang Huo (ASICON, 2015)

A 1G-cell floating-gate NOR flash memory in 65 nm technology with 100 ns random access time. - Lifang Liu; Dong Wu; Xuemei Liu; Zongliang Huo; Ming Liu; Liyang Pan (Sci. China Inf. Sci., 2015)

A 1.2 mV ripple, 4.5 V charge pump using controllable pumping current technology. - Cece Huang; Yu Wang 097; Teng Chen; Liyin Fu; Qi Wang 041; Zongliang Huo (IEICE Electron. Express, 2017)

Dynamic LLR scheme based on EM algorithm for LDPC decoding in NAND flash memory. - Junli Peng; Qi Wang 041; Xiang Fu; Zongliang Huo (IEICE Electron. Express, 2017)

A fast read retry method for 3D NAND flash memories using novel valley search algorithm. - Qianhui Li; Qi Wang 041; Qikang Xu; Zongliang Huo (IEICE Electron. Express, 2018)

Word line interference based data recovery technique for 3D NAND Flash. - Liu Yang; Fei Liu; Huamin Cao; Qi Wang 041; Zongliang Huo (IEICE Electron. Express, 2018)

Cycling Induced Trap Generation and Recovery Near the Top Select Gate Transistor in 3D NAND. - Xingqi Zou; Liang Yan; Lei Jin; Da Li; Feng Xu; Di Ai; An Zhang 008; Hongtao Liu; Ming Wang; Wei Li; Yali Song; Huazheng Wei; et al. (IRPS, 2019)

Adaptive Pulse Program Scheme to Improve the Vth Distribution for 3D NAND Flash. - Shuang Li; Zhichao Du; Yu Wang 097; Fei Liu; Qi Wang 041; Zongliang Huo (ISCAS, 2020)

An Improved Dimensional Measurement Method of Staircase Patterns With Higher Precision in 3D NAND. - Peizhen Hong; Zhiguo Zhao; Jun Luo 002; Zhiliang Xia; Xiaojing Su; Libin Zhang; Chunlong Li; Zongliang Huo (IEEE Access, 2020)

Multi-Coding ECC Algorithm Based on 3D Charge Trap NAND Flash Hot Region Cell Prediction. - Yiyang Jiang; Qi Wang 041; Qianhui Li; Zongliang Huo (IEEE Commun. Lett., 2020)

A Small Ripple Program Voltage Generator Without High-Voltage Regulator for 3D NAND Flash. - Cece Huang; Fei Liu; Qianqian Wang; Zongliang Huo (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

LAEPS: LDPC LLR Adaptive Estimation Based on Pattern Set Distribution Variation in 3D Charge Trap NAND Flash Memories. - Qianhui Li; Yiyang Jiang; Qi Wang 041; Liu Yang; Zexia Wang; Xiaolei Yu; Jing He 020; Zongliang Huo (ICTA, 2021)

Using Word Line (WL) Interference to Reduce Refresh Operations on 3D NAND Flash System. - Liu Yang; Qi Wang 041; Qianhui Li; Xiaolei Yu; Zongliang Huo (ICTA, 2021)

Efficient Data Recovery Technique for 3D TLC NAND Flash Memory based on WL Interference. - Liu Yang; Qi Wang 041; Qianhui Li; Xiaolei Yu; Jing He 020; Zongliang Huo (IRPS, 2021)

Low Power Program Scheme With Capacitance-Less Charge Recycling for 3D NAND Flash Memory. - Cece Huang; Fei Liu; Qianqian Wang; Zongliang Huo (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A Small Ripple and High-Efficiency Wordline Voltage Generator for 3-D nand Flash Memories. - Qianqian Wang; Fei Liu; Cece Huang; Qianhui Li; Zongliang Huo (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Unleash Scaling Potential of 3D NAND with Innovative Xtacking® Architecture. - Zongliang Huo; Weihua Cheng; Simon Yang (VLSI Technology and Circuits, 2022)

Reduce Refresh Operations on 3-D TLC nand Flash System via Wordline (WL) Interference. - Liu Yang; Qi Wang 041; Qianhui Li; Xiaolei Yu; Zongliang Huo (IEEE Embed. Syst. Lett., 2022)

Gradual Channel Estimation Method for TLC NAND Flash Memory. - Liu Yang; Qi Wang 041; Qianhui Li; Xiaolei Yu; Jing He 020; Zongliang Huo (IEEE Embed. Syst. Lett., 2022)

A polynomial based valley search algorithm for 3D NAND flash memory. - Runze Li; Ye Tian; Zhichao Du; Yu Wang 097; Qi Wang 041; Zongliang Huo (IEICE Electron. Express, 2022)

A novel adaptive-refresh scheme to reduce refresh with page endurance variance in 3D TLC NAND flash memories. - Xianliang Wang; Qi Wang 041; Bo Zhang; Jing He 020; Zongliang Huo (IEICE Electron. Express, 2022)

FBEL: Enhanced LLR optimization algorithm based on the VSER prediction by flag bits in the bit-flipping scheme. - Bo Zhang; Qi Wang 041; Xiaolei Yu; Qianhui Li; Jing He 020; Xianliang Wang; Qianqi Zhao; Xuhong Qiang; Zongliang Huo; Tianchun Ye 001 (IEICE Electron. Express, 2023)

LIAD: A Method for Extending the Effective Time of 3-D TLC NAND Flash Hard Decision. - Xiaolei Yu; Jing He 020; Qianhui Li; Bo Zhang; Xianliang Wang; Liu Yang; Tian-Chun Ye 001; Qi Wang 041; Zongliang Huo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Interleaved LDPC Decoding Scheme Improves 3-D TLC NAND Flash Memory System Performance. - Xiaolei Yu; Jing He 020; Bo Zhang; Xianliang Wang; Qianhui Li; Qi Wang 041; Zongliang Huo; Tian-Chun Ye 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

DMMC: A Polar Code Construction Method for Improving Performance in TLC NAND Flash. - Xiaolei Yu; Jing He 020; Qianhui Li; Bo Zhang; Xianliang Wang; Qi Wang 041; Zongliang Huo (IEEE Embed. Syst. Lett., 2024)

Temperature Effects of Program Operation in 3-D nand Flash Memory: Observations, Analysis, and Solutions. - Hua Feng; Debao Wei; Qi Wang 041; Yongchao Wang; Liyan Qiao; Zongliang Huo (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

NV-APP: Invalid Programming Performance Improved No-Verify and Adaptive Pulse Programming Scheme for 3-D QLC nand Flash. - Qianqi Zhao; Jing He 020; Tong Qu; Wentian Wu; Qianhui Li; Qi Wang 041; Zongliang Huo; Tian-Chun Ye 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)