Layout dependency induced deviation from Poisson area scaling in BEOL dielectric reliability. - Yunlong Li; Zsolt Tökei; Philippe Roussel; Guido Groeseneken; Karen Maex (Microelectron. Reliab., 2005)

Reliability challenges for copper low-k dielectrics and copper diffusion barriers. - Zsolt Tökei; Yunlong Li; G. P. Beyer (Microelectron. Reliab., 2005)

Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design. - Antonis Papanikolaou; Miguel Miranda; Hua Wang; Francky Catthoor; M. Satyakiran; Pol Marchal; Ben Kaczer; C. Bruynseraede; Zsolt Tokei (VLSI-SoC, 2006)

A tool flow for predicting system level timing failures due to interconnect reliability degradation. - Jin Guo 001; Antonis Papanikolaou; Michele Stucchi; Kristof Croes; Zsolt Tokei; Francky Catthoor (ACM Great Lakes Symposium on VLSI, 2008)

Study of copper drift during TDDB of intermetal dielectrics by using fully passivated MOS capacitors as test vehicle. - Kristof Croes; G. Cannatá; L. Zhao; Zsolt Tökei (Microelectron. Reliab., 2008)

Design Technology co-optimization for N10. - Julien Ryckaert; Praveen Raghavan; Rogier Baert; Marie Garcia Bardon; Mircea Dusa; Arindam Mallik; Sushil Sakhare; Boris Vandewalle; Piet Wambacq; Bharani Chava; Kris Croes; Morin Dehan; et al. (CICC, 2014)

Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies. - Trong Huynh Bao; Dmitry Yakimets; Julien Ryckaert; Ivan Ciofi; Rogier Baert; Anabela Veloso; Jürgen Bömmels; Nadine Collaert; Philippe Roussel; S. Demuynck; Praveen Raghavan; Abdelkarim Mercha; et al. (ESSDERC, 2014)

As-grown donor-like traps in low-k dielectrics and their impact on intrinsic TDDB reliability. - Baojun Tang; Kris Croes; Yohan Barbarin; Yunqi Wang; Robin Degraeve; Yunlong Li; Maria Toledano-Luque; Thomas Kauerauf; Jürgen Bömmels; Zsolt Tökei; Ingrid De Wolf (Microelectron. Reliab., 2014)

Chip-Package Interaction in 3D stacked IC packages using Finite Element Modelling. - Bart Vandevelde; Andrej Ivankovic; B. Debecker; Melina Lofrano; Kris Vanstreels; Wei Guo; Vladimir Cherman; Marcel Gonzalez; Geert Van der Plas; Ingrid De Wolf; Eric Beyne; Zsolt Tokei (Microelectron. Reliab., 2014)

Holisitic device exploration for 7nm node. - Praveen Raghavan; Marie Garcia Bardon; Doyoung Jang; P. Schuddinck; Dmitry Yakimets; Julien Ryckaert; Abdelkarim Mercha; Naoto Horiguchi; Nadine Collaert; Anda Mocuta; Dan Mocuta; Zsolt Tokei; et al. (CICC, 2015)

Impact of interconnect multiple-patterning variability on SRAMs. - Ioannis Karageorgos; Michele Stucchi; Praveen Raghavan; Julien Ryckaert; Zsolt Tokei; Diederik Verkest; Rogier Baert; Sushil Sakhare; Wim Dehaene (DATE, 2015)

Impact of process variability on BEOL TDDB lifetime model assessment. - Kris Croes; Deniz Kocaay; Ivan Ciofi; Jürgen Bömmels; Zsolt Tökei (IRPS, 2015)

Intrinsic reliability of local interconnects for N7 and beyond. - Kris Croes; Alicja Lesniewska; Chen Wu; Ivan Ciofi; Agnieszka Banczerowska; B. Briggs; S. Demuynck; Zsolt Tökei; Jürgen Bömmels; Yves Saad; W. Gao (IRPS, 2015)

Constant voltage electromigration for advanced BEOL copper interconnects. - Baojun Tang; Kris Croes; Nicolas Jourdan 002; Jürgen Bömmels; Zsolt Tökei; Ingrid De Wolf; Eric Wilcox; Timothy McMullen (IRPS, 2015)

Technology/circuit co-optimization and benchmarking for graphene interconnects at Sub-10nm technology node. - Chenyun Pan; Praveen Raghavan; Francky Catthoor; Zsolt Tokei; Azad Naeemi (ISQED, 2015)

Evaluation of via density and low-k Young's modulus influence on mechanical performance of advanced node multi-level Back-End-Of-Line. - Luka Kljucar; Mario Gonzalez; Ingrid De Wolf; Kristof Croes; Jürgen Bömmels; Zsolt Tökei (Microelectron. Reliab., 2016)

Design considerations for the mechanical integrity of airgaps in nano-interconnects under chip-package interaction; a numerical investigation. - Houman Zahedmanesh; Mario Gonzalez; Ivan Ciofi; Kristof Croes; Jürgen Bömmels; Zsolt Tökei (Microelectron. Reliab., 2016)

Impact of via density and passivation thickness on the mechanical integrity of advanced Back-End-Of-Line interconnects. - Luka Kljucar; Mario Gonzalez; Kristof Croes; Ingrid De Wolf; Joke De Messemaeker; Gayle Murdoch; Philip Nolmans; Joeri De Vos; Jürgen Bömmels; Eric Beyne; Zsolt Tökei (Microelectron. Reliab., 2017)

Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond. - Trong Huynh Bao; Julien Ryckaert; Zsolt Tokei; Abdelkarim Mercha; Diederik Verkest; Aaron Voon-Yew Thean; Piet Wambacq (IEEE Trans. Very Large Scale Integr. Syst., 2017)

The first observation of p-type electromigration failure in full ruthenium interconnects. - Sofie Beyne; Shibesh Dutta; Olalla Varela Pedreira; Niels Bosman; Christoph Adelmann; Ingrid De Wolf; Zsolt Tökei; Kristof Croes (IRPS, 2018)

Stress mitigation of 3D-stacking/packaging induced stresses. - Kristof Croes; Vladimir Cherman; Melina Lofrano; Houman Zahedmanesh; Luka Kljucar; Mario Gonzalez; Ingrid De Wolf; Zsolt Tökei; Eric Beyne (IRPS, 2018)

Insights into metal drift induced failure in MOL and BEOL. - Chen Wu; O. Varela Pedreira; Alicja Lesniewska; Yunlong Li; Ivan Ciofi; Zsolt Tökei; Kris Croes (IRPS, 2018)

Low-Frequency Noise Measurements to Characterize Cu-Electromigration Down to 44nm Metal Pitch. - Sofie Beyne; Olalla Varela Pedreira; Ingrid De Wolf; Zsolt Tökei; Kristof Croes (IRPS, 2019)

Dielectric Reliability Study of 21 nm Pitch Interconnects with Barrierless Ru Fill. - Alicja Lesniewska; Philippe J. Roussel; Davide Tierno; Victor Vega-Gonzalez; Marleen H. van der Veen; Patrick Verdonck; Nicolas Jourdan 002; Christopher J. Wilson; Zsolt Tökei; Kris Croes (IRPS, 2020)

Metal reliability mechanisms in Ruthenium interconnects. - Olalla Varela Pedreira; Michele Stucchi; Anshul Gupta; Victor Vega-Gonzalez; Marleen van der Veen; Stephane Lariviere; Christopher J. Wilson; Zsolt Tökei; Kristof Croes (IRPS, 2020)

Global Is the New Local: FPGA Architecture at 5nm and Beyond. - Stefan Nikolic 001; Francky Catthoor; Zsolt Tokei; Paolo Ienne (FPGA, 2021)

Reliability of a DME Ru Semidamascene scheme with 16 nm wide Airgaps. - Alicja Lesniewska; Olalla Varela Pedreira; Melina Lofrano; Gayle Murdoch; Marleen H. van der Veen; Anish Dangol; Naoto Horiguchi; Zsolt Tökei; Kris Croes (IRPS, 2021)

Electromigration limits of copper nano-interconnects. - Houman Zahedmanesh; Olalla Varela Pedreira; Zsolt Tokei; Kristof Croes (IRPS, 2021)

Logic Scaling Options for the Next 10 Years: From FinFet to CFET, from Dual Damascene to Semi Damascene. - Zsolt Tokei (FPGA, 2022)

First demonstration of Two Metal Level Semi-damascene Interconnects with Fully Self-aligned Vias at 18MP. - Gayle Murdoch; Matin O'Toole; Giulio Marti; Ankit Pokhrel; Diana Tsvetanova; Stefan Decoster; Shreya Kundu; Yusuke Oniki; Arame Thiam; Quoc Toan Le; Olalla Varela Pedreira; Alicja Lesniewska; et al. (VLSI Technology and Circuits, 2022)

Electromigration-aware design technology co-optimization for SRAM in advanced technology nodes. - Mahta Mayahinia; Hsiao-Hsuan Liu; Subrat Mishra; Zsolt Tokei; Francky Catthoor; Mehdi B. Tahoori (DATE, 2023)

Technology/Memory Co-Design and Co-Optimization Using E-Tree Interconnect. - Zhenlin Pei; Mahta Mayahinia; Hsiao-Hsuan Liu; Mehdi B. Tahoori; Francky Catthoor; Zsolt Tokei; Chenyun Pan (ACM Great Lakes Symposium on VLSI, 2023)

Towards accurate temperature prediction in BEOL for reliability assessment (Invited). - Melina Lofrano; Herman Oprins; Xinyue Chang; Bjorn Vermeersch; Olalla Varela Pedreira; Alicja Lesniewska; Vladimir Cherman; Ivan Ciofi; Kristof Croes; Seongho Park; Zsolt Tokei (IRPS, 2023)

Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access. - Zhenlin Pei; Mahta Mayahinia; Hsiao-Hsuan Liu; Mehdi B. Tahoori; Shairfe Muhammad Salahuddin; Francky Catthoor; Zsolt Tokei; Chenyun Pan (ISQED, 2023)

Integration of a Stacked Contact MOL for Monolithic CFET. - Victor Vega-Gonzalez; D. Radisic; Bt Chan; S. Choudhury; S. Wang; A. Mingardi; Q. Toan Le; H. Decoster; Yusuke Oniki; P. Puttarame; Kevin Vandersmissen; J. P. Soulie; et al. (VLSI Technology and Circuits, 2023)

Mitigating Line-Break Defectivity with a Sandwiched TiN or W Layer for Metal Pitch 18 NM Aspect Ratio 6 Semi-Damascene Interconnects. - Anshul Gupta; Shreya Kundu; Stefan Decoster; K. Sah; G. Delie; B. Truijen; Davide Tierno; Giulio Marti; O. Varela Pedreira; B. Kenens; Y. Hermans; C. Adelmann; et al. (VLSI Technology and Circuits, 2024)

Ultra-Scaled E-Tree-Based SRAM Design and Optimization With Interconnect Focus. - Zhenlin Pei; Hsiao-Hsuan Liu; Mahta Mayahinia; Mehdi B. Tahoori; Francky Catthoor; Zsolt Tokei; Dawit Burusie Abdi; James Myers; Chenyun Pan (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Dynamic Segmented Bus for Energy-Efficient Last-Level Cache in Advanced Interconnect-Dominant Nodes. - Mahta Mayahinia; Tommaso Marinelli; Zhenlin Pei; Hsiao-Hsuan Liu; Chenyun Pan; Zsolt Tokei; Francky Catthoor; Mehdi B. Tahoori (IEEE Embed. Syst. Lett., 2024)

Leakage and TDDB Mechanisms in 18 nm Pitch Direct Metal Etch Ru Interconnects with Airgaps. - Alicja Lesniewska; Y. Fang; G. Delie; Philippe Roussel; Koen Van Sever; Emmanuel Chery; O. Varela Pedreira; Ivan Ciofi; S. H. Park; Zsolt Tokei; Kris Croes (IRPS, 2025)