Self-Dithered Digital Delta-Sigma Modulators for Fractional-N PLL. - Zule Xu; Jun Gyu Lee 001; Shoichi Masui (IEICE Trans. Electron., 2011)

Loop Design Optimization of Fourth-Order Fractional-N PLL Frequency Synthesizers. - Jun Gyu Lee 001; Zule Xu; Shoichi Masui (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

A 0.84ps-LSB 2.47mW time-to-digital converter using charge pump and SAR-ADC. - Zule Xu; Seungjong Lee; Masaya Miyahara; Akira Matsuzawa (CICC, 2013)

A 1 ps-resolution integrator-based time-to-digital converter using a SAR-ADC in 90nm CMOS. - Zule Xu; Masaya Miyahara; Akira Matsuzawa (NEWCAS, 2013)

A 0.5-to-1 V 9-bit 15-to-90 MS/s digitally interpolated pipelined-SAR ADC using dynamic amplifier. - James Lin; Zule Xu; Masaya Miyahara; Akira Matsuzawa (A-SSCC, 2014)

A 3.6 GHz fractional-N digital PLL using SAR-ADC-based TDC with-110 dBc/Hz in-band phase noise. - Zule Xu; Masaya Miyahara; Akira Matsuzawa (A-SSCC, 2015)

Sub-Picosecond Resolution and High-Precision TDC for ADPLLs Using Charge Pump and SAR-ADC. - Zule Xu; Seungjong Lee; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

A 2 GHz 3.1 mW type-I digital ring-based PLL. - Zule Xu; Anugerah Firdauzi; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (ESSCIRC, 2016)

A 74.9 dB SNDR 1 MHz bandwidth 0.9 mW delta-sigma time-to-digital converter using charge pump and SAR ADC. - Anugerah Firdauzi; Zule Xu; Masaya Miyahara; Akira Matsuzawa (ISCAS, 2016)

Synthesis and Automatic Layout of Resistive Digital-to-Analog Converter Based on Mixed-Signal Slice Cell. - Mitsutoshi Sugawara; Kenji Mori; Zule Xu; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016)

A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC. - Zule Xu; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (IEEE J. Solid State Circuits, 2016)

High Resolution Mixed-Domain Delta-Sigma Time-to-Digital Converter Using Compensated Charge-Pump Integrator. - Anugerah Firdauzi; Zule Xu; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Electron., 2017)

Robustness Evaluation of Restricted Boltzmann Machine against Memory and Logic Error. - Yasushi Fukuda; Zule Xu; Takayuki Kawahara (IEICE Trans. Electron., 2017)

Physical-Weight-Based Measurement Methodology Suppressing Noise or Reducing Test Time for High-Resolution Low-Speed ADCs. - Mitsutoshi Sugawara; Zule Xu; Akira Matsuzawa (IEICE Trans. Electron., 2017)

A Saturating-Integrator-Based Behavioral Model of Ring Oscillator Facilitating PLL Design. - Zule Xu; Takayuki Kawahara (IEICE Trans. Electron., 2017)

An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator based Frequency Synthesizer and Digital Background EVM Calibration. - Bangan Liu; Yuncheng Zhang; Junjun Qiu; Wei Deng 001; Zule Xu; Haosheng Zhang; Jian Pang; Yun Wang 008; Rui Wu 001; Teruki Someya; Atsushi Shirane; Kenichi Okada 001 (CICC, 2019)

A 0.0053-mm2 6-bit Fully-Standard-Cell-Based Synthesizable SAR ADC in 65 nm CMOS. - Naoki Ojima; Zule Xu; Tetsuya Iizuka (NEWCAS, 2019)

A compact quick-start sub-mW pulse-width-controlled PLL with automated layout synthesis using a place-and-route tool. - Wang Jing; Tetsuya Iizuka; Zule Xu; Toru Nakura (IEICE Electron. Express, 2019)

Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector. - Zule Xu; Anugerah Firdauzi; Masaya Miyahara; Kenichi Okada 001; Akira Matsuzawa (IEICE Trans. Electron., 2019)

A 3.2-to-3.8GHz Calibration-Free Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving -66dBc Worst-Case In-Band Fractional Spur. - Masaru Osada; Zule Xu; Tetsuya Iizuka (VLSI Circuits, 2020)

A 0.79-1.16-GHz Synthesizable Fractional-N PLL Using DTC-Based Multi-Stage Injection with Dithering-Assisted Local Skew Calibration Achieving -232.8-dB FoMref. - Zule Xu (A-SSCC, 2021)

A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur. - Zule Xu; Masaru Osada; Tetsuya Iizuka (VLSI Circuits, 2021)

An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC. - Zule Xu; Naoki Ojima; Shuowei Li; Tetsuya Iizuka (IEEE Trans. Very Large Scale Integr. Syst., 2021)

An Inductorless Fractional-N PLL Using Harmonic-Mixer-Based Dual Feedback and High-OSR Delta-Sigma-Modulator with Phase-Domain Filtering. - Masaru Osada; Zule Xu; Tetsuya Iizuka (ESSCIRC, 2022)

A Charge-Redistribution Multi-Bit Stochastic-Resonance ADC Enhancing SNDR for Weak Input Signal. - Ryoya Shibata; Zule Xu; Yasushi Hotta; Hitoshi Tabata; Tetsuya Iizuka (ISCAS, 2022)

A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter. - Zunsong Yang; Zule Xu; Masaru Osada; Tetsuya Iizuka (VLSI Technology and Circuits, 2022)

A Fractional-N Synthesizable PLL Using DTC-Based Multistage Injection With Dithering-Assisted Local Skew Calibration. - Zule Xu (IEEE J. Solid State Circuits, 2022)

Analysis of Offset Spurs in Phase-Locked-Loops Employing Harmonic-Mixer-Based Feedback With Sample-and-Hold Operation. - Masaru Osada; Zule Xu; Ryoya Shibata; Tetsuya Iizuka (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Quick Startup Low-Power Hybrid Crystal Oscillator for IoT Applications. - Masaya Miyahara; Zule Xu; Takehito Ishii; Noritoshi Kimura (IEICE Trans. Electron., 2023)

23.5 A 7.6mW IR-UWB Receiver Achieving -13dBm Blocker Resilience with a Linear RF Front-End. - Anoop Narayan Bhat; Paul Mateman; Zule Xu; Peter Vis; Paul Detterer; Gururaja Kasanadi Ramachandra; Yunus Baykal; Mario Konijnenburg; Yao-Hong Liu; Christian Bachmann; Peng Zhang 028 (ISSCC, 2024)

A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual-Feedback and Split-Feedback Frequency Division With Phase-Domain Filtering. - Masaru Osada; Zule Xu; Zunsong Yang; Tetsuya Iizuka (IEEE J. Solid State Circuits, 2024)

A 7.6-mW IR-UWB Receiver Achieving -17-dBm Blocker Resilience With a Linear RF Front-End. - Anoop Narayan Bhat; Paul Mateman; Zule Xu; Peter Vis; Paul Detterer; Gururaja Kasanadi Ramachandra; Yunus Baykal; Mario Konijnenburg; Yao-Hong Liu; Christian Bachmann; Peng Zhang 028 (IEEE J. Solid State Circuits, 2024)