A 0.003-mm2 440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS. - Zunsong Yang; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (A-SSCC, 2019)

A 25.4-to-29.5GHz 10.2mW Isolated Sub-Sampling PLL Achieving -252.9dB Jitter-Power FoM and -63dBc Reference Spur. - Zunsong Yang; Yong Chen 005; Shiheng Yang; Pui-In Mak; Rui Paulo Martins (ISSCC, 2019)

A 0.0071-mm2 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis. - Yong Chen 005; Pui-In Mak; Zunsong Yang; Chirn Chye Boon; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector. - Zunsong Yang; Yong Chen 005; Shiheng Yang; Pui-In Mak; Rui Paulo Martins (IEEE Access, 2020)

A 0.003-mm2 440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS. - Zunsong Yang; Yong Chen 005; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 10-GHz Inductorless Cascaded PLL with Zero-ISF Subsampling Phase Detector Achieving -63-dBc Reference Spur, 175-fs RMS Jitter and -240-dB FOMjitter. - Zunsong Yang; Zule Xu; Masaru Osada; Tetsuya Iizuka (VLSI Technology and Circuits, 2022)

A 3.3-GHz Integer N-Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving -82.2-dBc REF Spur and -255-dB FOM. - Zunsong Yang; Yong Chen 005; Jia Yuan; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Design of 1-5 GHz Two-Stage Noise-Canceling Low-Noise Amplifier with gm-boosting Technique for Spin Wave Detection Circuit. - Zhenyu Cheng 003; Zunsong Yang; Yuyang Zhu; Md Shamim Sarker; Hiroyasu Yamahara; Munetoshi Seki; Hitoshi Tabata; Tetsuya Iizuka (ICICDT, 2023)

A 1-5GHz Inverter-Based Phase Interpolator with All Digital Control for Spin-Wave Detection Circuit. - Yuyang Zhu; Zunsong Yang; Zhenyu Cheng 003; Md Shamim Sarker; Hiroyasu Yamahara; Munetoshi Seki; Hitoshi Tabata; Tetsuya Iizuka (ICICDT, 2023)

A Reference-Sampling PLL with Low-Ripple Double-Sampling PD Achieving -80-dBc Reference Spur and -259-dB FoM with 12-pF Input Load. - Zunsong Yang; Masaru Osada; Shuowei Li; Yuyang Zhu; Tetsuya Iizuka (VLSI Technology and Circuits, 2023)

7.4 A 0.027mm2 5.6-7.8GHz Ring-Oscillator-Based Ping-Pong Sampling PLL Scoring 220.3fsrms Jitter and -74.2dBc Reference Spur. - Yunbo Huang; Yong Chen 005; Zunsong Yang; Rui Paulo Martins; Pui-In Mak (ISSCC, 2024)

A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter, and -76.5-dBc Reference Spur. - Tianle Chen; Hongyu Ren; Zunsong Yang; Yunbo Huang; Xianghe Meng; Weiwei Yan; Weidong Zhang; Xuqiang Zheng; Xuan Guo; Tetsuya Iizuka; Pui-In Mak; Yong Chen 005; et al. (VLSI Technology and Circuits, 2024)

Investigation and Improvement on Self-Dithered MASH ΔΣ Modulator for Fractional-N Frequency Synthesis. - Yuyang Zhu; Zunsong Yang; Masaru Osada; Haoming Zhang; Tetsuya Iizuka (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024)

A Fractional-N Ring PLL Using Harmonic-Mixer-Based Dual-Feedback and Split-Feedback Frequency Division With Phase-Domain Filtering. - Masaru Osada; Zule Xu; Zunsong Yang; Tetsuya Iizuka (IEEE J. Solid State Circuits, 2024)

Design of a 1-5GHz Inverter-Based Phase Interpolator for Spin-Wave Detection. - Yuyang Zhu; Zunsong Yang; Zhenyu Cheng 003; Md Shamim Sarker; Hiroyasu Yamahara; Munetoshi Seki; Hitoshi Tabata; Tetsuya Iizuka (ASP-DAC, 2025)

A 22.4-25.6GHz Ping-Pong Sub-Sampling PLL Featuring Unified Supply Voltage and Balanced 2nd Harmonic Extraction Achieving 45.8fsrms Jitter and -254.3dB FoM. - Yunbo Huang; Zunsong Yang; Hongyu Ren; Rui Paulo Martins; Yan Lu 002; Nan Sun 001; Nan Qi; Yong Chen 005 (CICC, 2025)

A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Utilizing a Complementary-Injection Scheme and an Adaptive Pulsewidth Adjustment. - Zedong Wang; Xuqiang Zheng; Yu He; Hua Xu; Sai Li; Zunsong Yang; Fangxu Lv; Mingche Lai; Xinyu Liu 004 (IEEE J. Solid State Circuits, 2025)

An All-Standard-Cell-Based Synthesizable SAR ADC with Inverter-Cell-Based Capacitive DAC. - Shuowei Li; Zunsong Yang; Tetsuya Iizuka (Circuits Syst. Signal Process., 2025)