An all-digital de-skew clock generator for arbitrary wide range delay. - Kevin Fong; Yu-Cheng Hung; Zuow-Zun Chen; Tai-Cheng Lee (APCCAS, 2010)

The Design and Analysis of Dual-Delay-Path Ring Oscillators. - Zuow-Zun Chen; Tai-Cheng Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

The Study of a Dual-Mode Ring Oscillator. - Zuow-Zun Chen; Tai-Cheng Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

14.9 Sub-sampling all-digital fractional-N frequency synthesizer with -111dBc/Hz in-band phase noise and an FOM of -242dB. - Zuow-Zun Chen; Yen-Hsiang Wang; Jaewook Shin; Yan Zhao 002; Seyed Arash Mirhaj; Yen-Cheng Kuan; Huan-Neng Ron Chen; Chewnpu Jou; Ming-Hsien Tsai 002; Fu-Lung Hsueh; Mau-Chung Frank Chang (ISSCC, 2015)

6.7 A 2.3mW 11cm-range bootstrapped and correlated-double-sampling (BCDS) 3D touch sensor for mobile devices. - Li Du; Yan Zhang 050; Frank Hsiao; Adrian Tang 002; Yan Zhao 002; Yilei Li; Zuow-Zun Chen; Liting Huang; Mau-Chung Frank Chang (ISSCC, 2015)

2.1 An integrated 0.56THz frequency synthesizer with 21GHz locking range and -74dBc/Hz phase noise at 1MHz offset in 65nm CMOS. - Yan Zhao 002; Zuow-Zun Chen; Gabriel Virbila; Yinuo Xu; Richard Al Hadi; Yanghyo Kim; Adrian Tang 002; Theodore Reck; Huan-Neng Ron Chen; Chewnpu Jou; Fu-Lung Hsueh; Mau-Chung Frank Chang (ISSCC, 2016)

Digital PLL for phase noise cancellation in ring oscillator-based I/Q receivers. - Zuow-Zun Chen; Yilei Li; Yen-Cheng Kuan; Boyu Hu; Chien-Heng Wong; Mau-Chung Frank Chang (VLSI Circuits, 2016)

A 16Gb/s 14.7mW tri-band cognitive serial link transmitter with forwarded clock to enable PAM-16 / 256-QAM and channel response detection in 28 nm CMOS. - Yuan Du; Wei-Han Cho; Yilei Li; Chien-Heng Wong; Jieqiong Du; Po-Tsang Huang; Yanghyo Kim; Zuow-Zun Chen; Sheau Jiung Lee; Mau-Chung Frank Chang (VLSI Circuits, 2016)

A 0.56 THz Phase-Locked Frequency Synthesizer in 65 nm CMOS Technology. - Yan Zhao 002; Zuow-Zun Chen; Yuan Du; Yilei Li; Richard Al Hadi; Gabriel Virbila; Yinuo Xu; Yanghyo Kim; Adrian Tang 002; Theodore Reck; Mau-Chung Frank Chang (IEEE J. Solid State Circuits, 2016)

An 8-Bit Compressive Sensing ADC With 4-GS/s Equivalent Speed Utilizing Self-Timed Pipeline SAR-Binary-Search. - Boyu Hu; Fengbo Ren; Zuow-Zun Chen; Xicheng Jiang; Mau-Chung Frank Chang (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

DPLL for Phase Noise Cancellation in Ring Oscillator-Based Quadrature Receivers. - Zuow-Zun Chen; Yen-Cheng Kuan; Yilei Li; Boyu Hu; Chien-Heng Wong; Mau-Chung Frank Chang (IEEE J. Solid State Circuits, 2017)