On Decomposition of Multi-Valued Switching Functions. - K. M. Waliuzzaman; Zvonko G. Vranesic (Comput. J., 1970)

A Many-Valued Algebra for Switching Systems. - Zvonko G. Vranesic; E. Stewart Lee; Kenneth C. Smith (IEEE Trans. Computers, 1970)

Ternary logic in parallel multipliers. - Zvonko G. Vranesic; V. Carl Hamacher (Comput. J., 1972)

Functional Transformation in Simplification of Multivalued Switching Functions. - Zvonko G. Vranesic; K. M. Waliuzzaman (IEEE Trans. Computers, 1972)

Design of a Fully Variable - Length Structured Minicomputer. - Zvonko G. Vranesic; V. Carl Hamacher; Y. Y. Leung (ISCA, 1973)

Engineering aspects of multi-valued logic systems. - Zvonko G. Vranesic; Kenneth C. Smith (Computer, 1974)

Application of Multithreshold Elements in the Realization of Many-Valued Logic Networks. - A. Druzeta; Zvonko G. Vranesic; A. S. Sedra (IEEE Trans. Computers, 1974)

Fault Detection of Binary Sequential Machines Using R-Valued Test Machines. - Donald A. Sheppard; Zvonko G. Vranesic (IEEE Trans. Computers, 1974)

Experiences with CHUTE. - F. M. Valenti; Zvonko G. Vranesic (ACM Annual Conference, 1977)

Multiple-Valued Logic: An Introduction and Overview. - Zvonko G. Vranesic (IEEE Trans. Computers, 1977)

Review of Content addressable parallel processors by Caxton C. Foster. Van Nostrand Reinhold Co. 1976. - Zvonko G. Vranesic (SIGARCH Comput. Archit. News, 1978)

A. Higher Radix Technique for Fault Detection in Many-Valued Multithreshold Networks. - A. Druzeta; Zvonko G. Vranesic (IEEE Trans. Computers, 1978)

Teaching Computer Structures. - Zvonko G. Vranesic; Kenneth J. Thurber; Sperry Univac (Computer, 1980)

Ternary Rate-Multipliers. - Hussein T. Mouftah; Kenneth C. Smith; Zvonko G. Vranesic (IEEE Trans. Computers, 1980)

TORNET: A local area network. - Zvonko G. Vranesic; V. Carl Hamacher; Wayne M. Loucks; Safwat G. Zaky (SIGCOMM, 1981)

Key compression using segment strings. - C. L. Lam; Zvonko G. Vranesic (Inf. Syst., 1981)

On fault detection in CMOS logic networks. - Kuang-Wei Chiang; Zvonko G. Vranesic (DAC, 1983)

A Tree Representation of Combinational Networks. - Kuang-Wei Chiang; Zvonko G. Vranesic (IEEE Trans. Computers, 1983)

A Pipelined Distributed Arithmetic PFFT Processor. - Paul Chow; Zvonko G. Vranesic; Jui Lin Yen (IEEE Trans. Computers, 1983)

Comments on "Fault Diagnosis of MOS Combinational Networks". - Kuang-Wei Chiang; Zvonko G. Vranesic (IEEE Trans. Computers, 1984)

FERMTOR: A Tunable Multiprocessor Architecture. - Jonathan Rose; Wayne M. Loucks; Zvonko G. Vranesic (IEEE Micro, 1985)

Implementation of a Dynamic Address Assignment Protocol in a Local Area Network. - Wayne M. Loucks; William I. Kwak; Zvonko G. Vranesic (Comput. Networks, 1986)

Synthesis of Multivalued Multithreshold Functions for CCD Implementation. - Mostafa I. H. Abd-El-Barr; Safwat G. Zaky; Zvonko G. Vranesic (IEEE Trans. Computers, 1986)

Parallel standard cell placement algorithms with quality equivalent to simulated annealing. - Jonathan Rose; W. Martin Snelgrove; Zvonko G. Vranesic (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

Using active components to perform voltage division in digital-to-analog conversion. - Chu Phoon Chong; Kenneth C. Smith; Zvonko G. Vranesic (IEEE J. Solid State Circuits, 1989)

Computer organization, 3rd Edition. - V. Carl Hamacher; Zvonko G. Vranesic; Safwat G. Zaky (McGraw-Hill, 1990)

TORMLAN - A Multichannel Local Area Network Protocol. - Lap-kong Chan; Zvonko G. Vranesic (INFOCOM, 1990)

Step-Wise Synthesis of CCD MVL Functions. - Safwat G. Zaky; Zvonko G. Vranesic; Mostafa I. H. Abd-El-Barr (ISMVL, 1990)

Reusable motion synthesis using state-space controllers. - Michiel van de Panne; Eugene Fiume; Zvonko G. Vranesic (SIGGRAPH, 1990)

Cost Reduction in the CCD Realization of MVMT Function. - Mostafa I. H. Abd-El-Barr; Zvonko G. Vranesic (IEEE Trans. Computers, 1990)

Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs. - Robert J. Francis; Jonathan Rose; Zvonko G. Vranesic (DAC, 1991)

Technology Mapping on Lookup Table-Based FPGAs for Performance. - Robert J. Francis; Jonathan Rose; Zvonko G. Vranesic (ICCAD, 1991)

A Hybrid Token/Insertion Ring LAN. - Zvonko G. Vranesic; V. Carl Hamacher; A. K. Sanwalka; Safwat G. Zaky (INFOCOM, 1991)

On the Synthesis of 4-Valued Current Mode CMOS Circuits. - Konrad Lei; Zvonko G. Vranesic (ISMVL, 1991)

Hector: A Hierarchically Structured Shared-memory Multiprocessor. - Zvonko G. Vranesic; Michael Stumm; David M. Lewis; Ron White (Computer, 1991)

Algorithmic Synthesis of MVL Functions for CCD Implementation. - Mostafa I. H. Abd-El-Barr; Zvonko G. Vranesic; Safwat G. Zaky (IEEE Trans. Computers, 1991)

Towards the Realization of 4-Valued CMOS Circuits. - Konrad Lei; Zvonko G. Vranesic (ISMVL, 1992)

Cache Consistency in Hierarchical-Ring-Based Multiprocessors. - Keith I. Farkas; Zvonko G. Vranesic; Michael Stumm (SC, 1992)

A detailed router for field-programmable gate arrays. - Stephen Brown 003; Jonathan Rose; Zvonko G. Vranesic (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Current-Mode CMOS Galois Field Circuits. - Zeljko Zilic; Zvonko G. Vranesic (ISMVL, 1993)

Architectural Support for Block Transfers in a Shared-Memory Multiprocessor. - Steven J. E. Wilton; Zvonko G. Vranesic (SPDP, 1993)

Physically Based Modeling and Control of Turning. - Michiel van de Panne; Eugene Fiume; Zvonko G. Vranesic (CVGIP Graph. Model. Image Process., 1993)

A stochastic model to predict the routability of field-programmable gate arrays. - Stephen Dean Brown; Jonathan Rose; Zvonko G. Vranesic (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Performance Prediction for Different Consistency Schemes in Distributed Shared Memory Systems. - Sinisa Srbljic; Zvonko G. Vranesic; Leo Budin (HPDC, 1994)

On Scheduling in Multiprocessor Systems Using Fuzzy Logic. - Alireza Kaviani; Zvonko G. Vranesic (ISMVL, 1994)

Bidirectional Ring: An Alternative to the Hierarchy of Unidirectional Rings. - Muhammad Jaseemuddin; Zvonko G. Vranesic (Euro-Par, 1995)

Architecture of Centralized Field-Configurable Memory. - Steven J. E. Wilton; Jonathan Rose; Zvonko G. Vranesic (FPGA, 1995)

Reed-Muller Forms for Incompletely Specified Functions via Sparse Polynomial Interpolation. - Zeljko Zilic; Zvonko G. Vranesic (ISMVL, 1995)

A Multiple-Valued Reed-Muller Transform for Incompletely Specified Functions. - Zeljko Zilic; Zvonko G. Vranesic (IEEE Trans. Computers, 1995)

Scalable cache consistency for hierarchically structured multiprocessors. - Keith I. Farkas; Zvonko G. Vranesic; Michael Stumm (J. Supercomput., 1995)

Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools. - Stephen Brown 003; Naraig Manjikian; Zvonko G. Vranesic; S. Caranci; A. Grbic; R. Grindley; M. Gusat; K. Loveless; Zeljko Zilic; Sinisa Srbljic (DAC, 1996)

Using BDDs to Design ULMs for FPGAs. - Zeljko Zilic; Zvonko G. Vranesic (FPGA, 1996)

New Interpolation Algorithms for Multiple-Valued Reed-Muller Forms. - Zeljko Zilic; Zvonko G. Vranesic (ISMVL, 1996)

Minimizing FPGA Interconnect Delays. - Stephen Brown 003; Muhammad M. Khellah; Zvonko G. Vranesic (IEEE Des. Test Comput., 1996)

Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays. - Steven J. E. Wilton; Jonathan Rose; Zvonko G. Vranesic (FPGA, 1997)

Memory-System Design Considerations for Dynamically-Scheduled Processors. - Keith I. Farkas; Paul Chow; Norman P. Jouppi; Zvonko G. Vranesic (ISCA, 1997)

The Multicluster Architecture: Reducing Cycle Time Through Partitioning. - Keith I. Farkas; Paul Chow; Norman P. Jouppi; Zvonko G. Vranesic (MICRO, 1997)

Analytical Prediction of Performance for Cache Coherence Protocols. - Sinisa Srbljic; Zvonko G. Vranesic; Michael Stumm; Leo Budin (IEEE Trans. Computers, 1997)

Design and Implementation of the NUMAchine Multiprocessor. - A. Grbic; Stephen Brown 003; S. Caranci; R. Grindley; M. Gusat; Guy G. Lemieux; K. Loveless; Naraig Manjikian; Sinisa Srbljic; Michael Stumm; Zvonko G. Vranesic; Zeljko Zilic (DAC, 1998)

The FPGA Challenge. - Zvonko G. Vranesic (ISMVL, 1998)

Using Decision Diagrams to Design ULMs for FPGAs. - Zeljko Zilic; Zvonko G. Vranesic (IEEE Trans. Computers, 1998)

The Multicluster Architecture: Reducing Processor Cycle Time Through Partitioning. - Keith I. Farkas; Paul Chow; Norman P. Jouppi; Zvonko G. Vranesic (Int. J. Parallel Program., 1999)

The memory/logic interface in FPGAs with large embedded memory arrays. - Steven J. E. Wilton; Jonathan Rose; Zvonko G. Vranesic (IEEE Trans. Very Large Scale Integr. Syst., 1999)

The NUMAchine Multiprocessor. - R. Grindley; Tarek S. Abdelrahman; Stephen Brown 003; S. Caranci; D. DeVries; Benjamin Gamsa; A. Grbic; M. Gusat; R. Ho; Orran Krieger; Guy G. Lemieux; K. Loveless; et al. (ICPP, 2000)

Structural analysis and generation of synthetic digital circuits with memory. - Steven J. E. Wilton; Jonathan Rose; Zvonko G. Vranesic (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices. - Valavan Manohararajah; Terry P. Borer; Stephen Dean Brown; Zvonko G. Vranesic (FPL, 2002)

A Deterministic Multivariate Interpolation Algorithm for Small Finite Fields. - Zeljko Zilic; Zvonko G. Vranesic (IEEE Trans. Computers, 2002)

Use of HDLs in teaching of computer hardware courses. - Zvonko G. Vranesic; Stephen Brown 003 (WCAE, 2003)

A fast algorithm for OR-AND-OR synthesis. - Debatosh Debnath; Zvonko G. Vranesic (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Experiences with Soft-Core Processor Design. - Franjo Plavec; Blair Fort; Zvonko G. Vranesic; Stephen Dean Brown (IPDPS, 2005)

A Multithreaded Soft Processor for SoPC Area Reduction. - Blair Fort; Davor Capalija; Zvonko G. Vranesic; Stephen Dean Brown (FCCM, 2006)

Adaptive FPGAs: High-Level Architecture and a Synthesis Method. - Valavan Manohararajah; Stephen Dean Brown; Zvonko G. Vranesic (FPL, 2006)

Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping. - Valavan Manohararajah; Stephen Dean Brown; Zvonko G. Vranesic (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

On Digital Search Trees - A Simple Method for Constructing Balanced Binary Trees. - Franjo Plavec; Zvonko G. Vranesic; Stephen Brown 003 (ICSOFT (PL/DPS/KE/MUSE), 2007)

Towards Compilation of Streaming Programs into FPGA Hardware. - Franjo Plavec; Zvonko G. Vranesic; Stephen Brown 003 (FDL, 2008)

Stream Programming for FPGAs. - Franjo Plavec; Zvonko G. Vranesic; Stephen Brown 003 (FDL (Selected Papers), 2008)

Enhancements to FPGA design methodology using streaming. - Franjo Plavec; Zvonko G. Vranesic; Stephen Brown 003 (FPL, 2009)

Exploiting Task- and Data-Level Parallelism in Streaming Applications Implemented in FPGAs. - Franjo Plavec; Zvonko G. Vranesic; Stephen Brown 003 (ACM Trans. Reconfigurable Technol. Syst., 2013)