Francky Catthoor
Orcid: 0000-0002-3599-8515Affiliations:
- Catholic University of Leuven, Belgium
According to our database1,
Francky Catthoor
authored at least 739 papers
between 1988 and 2024.
Collaborative distances:
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on orcid.org
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on kuleuven.be
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on dl.acm.org
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Bibliography
2024
Flexible Unipolar IGZO Transistor-Based Integrate and Fire Neurons for Spiking Neuromorphic Applications.
IEEE Trans. Biomed. Circuits Syst., February, 2024
STDP-Driven Development of Attention-Based People Detection in Spiking Neural Networks.
IEEE Trans. Cogn. Dev. Syst., February, 2024
Improving the Representativeness of Simulation Intervals for the Cache Memory System.
IEEE Access, 2024
An Advanced Hybrid Boot-LSTM-ICSO-PP Approach for Day-Ahead Probabilistic PV Power Yield Forecasting and Intra-Hour Power Fluctuation Estimation.
IEEE Access, 2024
Proceedings of the IEEE International Reliability Physics Symposium, 2024
Thermal Analysis of High-Performance Server SoCs from FinFET to Nanosheet Technologies.
Proceedings of the IEEE International Reliability Physics Symposium, 2024
2023
IEEE Trans. Very Large Scale Integr. Syst., December, 2023
COMPAD: A heterogeneous cache-scratchpad CPU architecture with data layout compaction for embedded loop-dominated applications.
J. Syst. Archit., December, 2023
An Online-Spike-Sorting IC Using Unsupervised Geometry-Aware OSort Clustering for Efficient Embedded Neural-Signal Processing.
IEEE J. Solid State Circuits, November, 2023
Acceleration of Control Intensive Applications on Coarse-Grained Reconfigurable Arrays for Embedded Systems.
IEEE Trans. Computers, September, 2023
A memory footprint optimization framework for Python applications targeting edge devices.
J. Syst. Archit., September, 2023
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023
Improving the Accuracy of Spiking Neural Networks for Radar Gesture Recognition Through Preprocessing.
IEEE Trans. Neural Networks Learn. Syst., June, 2023
Thermal-Comfort Aware Online Co-Scheduling Framework for HVAC, Battery Systems, and Appliances in Smart Buildings.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., May, 2023
Exploring Pareto-Optimal Hybrid Main Memory Configurations Using Different Emerging Memories.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2023
IEEE Trans. Emerg. Top. Comput., 2023
A New Co-Optimized Hybrid Model Based on Multi-Objective Optimization for Probabilistic Wind Power Forecasting in a Spatio-Temporal Framework.
IEEE Access, 2023
Proceedings of the 10th ACM International Conference on Systems for Energy-Efficient Buildings, 2023
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023
Proceedings of the 20th ACM SIGPLAN International Conference on Managed Programming Languages and Runtimes, 2023
Proceedings of the Neuro-Inspired Computational Elements Conference, 2023
Exploring Information-Theoretic Criteria to Accelerate the Tuning of Neuromorphic Level-Crossing ADCs.
Proceedings of the Neuro-Inspired Computational Elements Conference, 2023
The Unexpected Efficiency of Bin Packing Algorithms for Dynamic Storage Allocation in the Wild: An Intellectual Abstract.
Proceedings of the 2023 ACM SIGPLAN International Symposium on Memory Management, 2023
Proceedings of the Active Inference - 4th International Workshop, 2023
A 384-Channel Online-Spike-Sorting IC Using Unsupervised Geo-OSort Clustering and Achieving 0.0013mm<sup>2</sup>/Ch and $1.78\mu \text{W/ch}$.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
Evaluating the Effects of FeFET Device Variability on Charge Sharing Based AiMC Accelerator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs).
Proceedings of the IEEE International Reliability Physics Symposium, 2023
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023
Fusing Event-based Camera and Radar for SLAM Using Spiking Neural Networks with Continual STDP Learning.
Proceedings of the IEEE International Conference on Robotics and Automation, 2023
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
Data Partition Optimization for High Energy Efficiency by Decoupling Local Dependence in Holographic Video Decoder.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Electromigration-aware design technology co-optimization for SRAM in advanced technology nodes.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
Wearable ECG-Derived Respiration Performance for Respiratory Monitoring with a Non-Standard ECG Lead.
Proceedings of the Computing in Cardiology, 2023
2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
Multitimescale Mitigation for Performance Variability Improvement in Time-Critical Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2022
84%-Efficiency Fully Integrated Voltage Regulator for Computing Systems Enabled by 2.5-D High-Density MIM Capacitor.
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Trans. Parallel Distributed Syst., 2022
Dynamic Quantization Range Control for Analog-in-Memory Neural Networks Acceleration.
ACM Trans. Design Autom. Electr. Syst., 2022
Breathing Pattern Estimation Using Wearable Bioimpedance for Assessing COPD Severity.
IEEE J. Biomed. Health Informatics, 2022
Microarchitectural Exploration of STT-MRAM Last-level Cache Parameters for Energy-efficient Devices.
ACM Trans. Embed. Comput. Syst., 2022
Time-Dependent Electromigration Modeling for Workload-Aware Design-Space Exploration in STT-MRAM.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Fail-Safe Human Detection for Drones Using a Multi-Modal Curriculum Learning Approach.
IEEE Robotics Autom. Lett., 2022
IEEE Micro, 2022
ACM J. Emerg. Technol. Comput. Syst., 2022
AERO: Design Space Exploration Framework for Resource-Constrained CNN Mapping on Tile-Based Accelerators.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
A Co-Simulation Methodology for the Design of Integrated Silicon Spin Qubits With Their Control/Readout Cryo-CMOS Electronics.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022
IEEE Des. Test, 2022
Investigating methods to improve photovoltaic thermal models at second-to-minute timescales.
CoRR, 2022
Learning to SLAM on the Fly in Unknown Environments: A Continual Learning Approach for Drones in Visually Ambiguous Scenes.
CoRR, 2022
Continuously Learning to Detect People on the Fly: A Bio-inspired Visual System for Drones.
CoRR, 2022
Predicting 6-minute walking test outcomes in patients with chronic obstructive pulmonary disease without physical performance measures.
Comput. Methods Programs Biomed., 2022
Scalable 1.4 μW cryo-CMOS SP4T multiplexer operating at 10 mK for high-fidelity superconducting qubit measurements.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
Learning to Encode Vision on the Fly in Unknown Environments: A Continual Learning SLAM Approach for Drones.
Proceedings of the IEEE International Symposium on Safety, Security, and Rescue Robotics, 2022
The Impact of Dynamic Storage Allocation on CPython Execution Time, Memory Footprint and Energy Consumption: An Empirical Study.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022
Proceedings of the IEEE International Test Conference, 2022
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022
Event Camera Data Classification Using Spiking Networks with Spike-Timing-Dependent Plasticity.
Proceedings of the International Joint Conference on Neural Networks, 2022
Learn to Learn on Chip: Hardware-aware Meta-learning for Quantized Few-shot Learning at the Edge.
Proceedings of the 7th IEEE/ACM Symposium on Edge Computing, 2022
Exploring Cross-fusion and Curriculum Learning for Multi-modal Human Detection on Drones.
Proceedings of the DroneSE and RAPIDO '22: System Engineering for constrained embedded systems, Budapest Hungary, January 17, 2022
Energy Consumption Evaluation of Optane DC Persistent Memory for Indexing Data Structures.
Proceedings of the 29th IEEE International Conference on High Performance Computing, 2022
The Effect of Walking on the Estimation of Breathing Pattern Parameters using Wearable Bioimpedance.
Proceedings of the 44th Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2022
Design of Many-Core Big Little µBrains for Energy-Efficient Embedded Neuromorphic Computing.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proactive Run-Time Mitigation for Time-Critical Applications Using Dynamic Scenario Methodology.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
VWR2A: a very-wide-register reconfigurable-array architecture for low-power embedded devices.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
Fast and Accurate Edge Computing Energy Modeling and DVFS Implementation in GEM5 Using System Call Emulation Mode.
J. Signal Process. Syst., 2021
High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2021
Combining Bioimpedance and Myographic Signals for the Assessment of COPD During Loaded Breathing.
IEEE Trans. Biomed. Eng., 2021
A Low-Complexity Radar Detector Outperforming OS-CFAR for Indoor Drone Obstacle Avoidance.
IEEE J. Sel. Top. Appl. Earth Obs. Remote. Sens., 2021
ConvSNN: A surrogate gradient spiking neural framework for radar gesture recognition.
Softw. Impacts, 2021
ACM J. Emerg. Technol. Comput. Syst., 2021
Enabling Resource-Aware Mapping of Spiking Neural Networks via Spatial Decomposition.
IEEE Embed. Syst. Lett., 2021
ACM Comput. Surv., 2021
Design of Many-Core Big Little μBrain for Energy-Efficient Embedded Neuromorphic Computing.
CoRR, 2021
Learning Event-based Spatio-Temporal Feature Descriptors via Local Synaptic Plasticity: A Biologically-realistic Perspective of Computer Vision.
CoRR, 2021
Power, Performance, Area and Cost Analysis of Memory-on-Logic Face-to-Face Bonded 3D Processor Designs.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE International Reliability Physics Symposium, 2021
NeuroXplorer 1.0: An Extensible Framework for Architectural Exploration with Spiking Neural Networks.
Proceedings of the ICONS 2021: International Conference on Neuromorphic Systems 2021, 2021
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021
Circuit Model for the Efficient Co-Simulation of Spin Qubits and their Control & Readout Circuitry.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
Proceedings of the 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2021
Detection of Respiratory Phases to Estimate Breathing Pattern Parameters using Wearable Bioimpendace.
Proceedings of the 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2021
Thermal Comfort Aware Online Energy Management Framework for a Smart Residential Building.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Memory Hierarchy Calibration Based on Real Hardware In-order Cores for Accurate Simulation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
J. Signal Process. Syst., 2020
Analysis of Functional Errors Produced by Long-Term Workload-Dependent BTI Degradation in Ultralow Power Processors.
IEEE Trans. Very Large Scale Integr. Syst., 2020
IEEE Trans. Very Large Scale Integr. Syst., 2020
A Retargetable MATLAB-to-C Compiler Exploiting Custom Instructions and Data Parallelism.
ACM Trans. Embed. Comput. Syst., 2020
ACM J. Emerg. Technol. Comput. Syst., 2020
IEEE Comput. Archit. Lett., 2020
Proceedings of the VLSI-SoC: Design Trends, 2020
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020
Memory Footprint Optimization Techniques for Machine Learning Applications in Embedded Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Physics based modeling of bimodal electromigration failure distributions and variation analysis for VLSI interconnects.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
Fast & Accurate Methodology for Aging Incorporation in Circuits using Adaptive Waveform Splitting (AWS).
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
PyCARL: A PyNN Interface for Hardware-Software Co-Simulation of Spiking Neural Network.
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020
Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020
Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic : (Special Session Paper).
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Cardiac Comorbidities in COPD Patients Explained Through HRV and Respiratory Indices.
Proceedings of the Computing in Cardiology, 2020
Relationship Between Heart Rate Recovery and Disease Severity in Chronic Obstructive Pulmonary Disease Patients.
Proceedings of the Computing in Cardiology, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
A Closed-Loop Controller to Ensure Performance and Temperature Constraints for Dynamic Applications.
ACM Trans. Embed. Comput. Syst., 2019
Fast Procedures for the Electrodeposition of Platinum Nanostructures on Miniaturized Electrodes for Improved Ion Sensing.
Sensors, 2019
Failure probability of a FinFET-based SRAM cell utilizing the most probable failure point.
Integr., 2019
A Framework to Explore Workload-Specific Performance and Lifetime Trade-offs in Neuromorphic Computing.
IEEE Comput. Archit. Lett., 2019
Wearable Bioimpedance Measurement for Respiratory Monitoring During Inspiratory Loading.
IEEE Access, 2019
A Synergy of a Closed-Loop DVFS Controller and CPU Hot-Plug For Run-Time Thermal Management in Multicore Systems.
Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019
Variation-Aware Physics-Based Electromigration Modeling and Experimental Calibration for VLSI Interconnects.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
Proceedings of the International Joint Conference on Neural Networks, 2019
A Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based LLCs.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019
Exploration of Segmented Bus As Scalable Global Interconnect for Neuromorphic Computing.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the 24th IEEE European Test Symposium, 2019
Analysis of Time Delay between Bioimpedance and Respiratory Volume Signals under Inspiratory Loaded Breathing.
Proceedings of the 41st Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
ACM Trans. Design Autom. Electr. Syst., 2018
IEEE Trans. Green Commun. Netw., 2018
Algorithm/Architecture Co-optimisation Technique for Automatic Data Reduction of Wireless Read-Out in High-Density Electrode Arrays.
ACM Trans. Embed. Comput. Syst., 2018
ACM Trans. Embed. Comput. Syst., 2018
Unsupervised heart-rate estimation in wearables with Liquid states and a probabilistic readout.
Neural Networks, 2018
A brief overview of gate oxide defect properties and their relation to MOSFET instabilities and device and circuit time-dependent variability.
Microelectron. Reliab., 2018
Techniques for dynamic hardware management of streaming media applications using a framework for system scenarios.
Microprocess. Microsystems, 2018
J. Low Power Electron., 2018
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018
Graceful Performance Adaption through Hardware-Software Interaction for Autonomous Battery Management of Multicore Smartphones.
Proceedings of the Ninth International Green and Sustainable Computing Conference, 2018
Proceedings of the 23rd IEEE European Test Symposium, 2018
Doping-free complementary inverter enabled by 2D WSe2 electrostatically-doped reconfigurable transistors.
Proceedings of the 76th Device Research Conference, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the Computer Information Systems and Industrial Management, 2018
Heartbeat Classification in Wearables Using Multi-layer Perceptron and Time-Frequency Joint Distribution of ECG.
Proceedings of the Third IEEE/ACM International Conference on Connected Health: Applications, 2018
2017
Impact and Mitigation of Sense Amplifier Aging Degradation Using Realistic Workloads.
IEEE Trans. Very Large Scale Integr. Syst., 2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
A MATLAB Vectorizing Compiler Targeting Application-Specific Instruction Set Processors.
ACM Trans. Design Autom. Electr. Syst., 2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Microprocess. Microsystems, 2017
IEEE Des. Test, 2017
Classification of Resilience Techniques Against Functional Errors at Higher Abstraction Layers of Digital Systems.
ACM Comput. Surv., 2017
Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Energy Efficient Adaptive Approach for Dependable Performance in the presence of Timing Interference.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
ACM Trans. Design Autom. Electr. Syst., 2016
Integrated Exploration Methodology for Data Interleaving and Data-to-Memory Mapping on SIMD Architectures.
ACM Trans. Embed. Comput. Syst., 2016
Near-Static Shading Exploration for Smart Photovoltaic Module Topologies Based on Snake-like Configurations.
ACM Trans. Embed. Comput. Syst., 2016
Data Flow Transformation for Energy-Efficient Implementation of Givens Rotation-Based QRD.
ACM Trans. Embed. Comput. Syst., 2016
Quantification of Sense Amplifier Offset Voltage Degradation due to Zero-and Run-Time Variability.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the International Conference on IC Design and Technology, 2016
Using an adaptive and time predictable runtime system for power-aware HPC-oriented applications.
Proceedings of the Seventh International Green and Sustainable Computing Conference, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Proceedings of the 21th IEEE European Test Symposium, 2016
Dynamic Hardware Management of the H264/AVC Encoder Control Structure Using a Framework for System Scenarios.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016
Approximating Standard Cell Delay Distributions by Reformulating the Most Probable Failure Point.
Proceedings of the Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the Near Threshold Computing, Technology, Methods and Applications., 2016
2015
Demonstrating HW-SW Transient Error Mitigation on the Single-Chip Cloud Computer Data Plane.
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
ACM Trans. Design Autom. Electr. Syst., 2015
Placement of Linked Dynamic Data Structures over Heterogeneous Memories in Embedded Systems.
ACM Trans. Embed. Comput. Syst., 2015
Comparison of NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes.
Microprocess. Microsystems, 2015
Classification Framework for Analysis and Modeling of Physically Induced Reliability Violations.
ACM Comput. Surv., 2015
IEEE Comput. Archit. Lett., 2015
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015
HARPA: Solutions for dependable performance under physically induced performance variability.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015
Technology/circuit co-optimization and benchmarking for graphene interconnects at Sub-10nm technology node.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Characterization of time-dependent variability using 32k transistor arrays in an advanced HK/MG technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Proceedings of the 10th International Design & Test Symposium, 2015
Impact of time-dependent variability on the yield and performance of 6T SRAM cells in an advanced HK/MG technology.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
The defect-centric perspective of device and circuit reliability - From individual defects to circuits.
Proceedings of the 45th European Solid State Device Research Conference, 2015
Proceedings of the 2015 International Conference on Embedded Software, 2015
System scenario framework evaluation on EFM32 using the H264/AVC encoder control structure.
Proceedings of the European Conference on Circuit Theory and Design, 2015
Comparative analysis of RD and Atomistic trap-based BTI models on SRAM Sense Amplifier.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015
Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015
Characterization and simulation methodology for time-dependent variability in advanced technologies.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
Configuration Mapping Algorithms to Reduce Energy and Time Reconfiguration Overheads in Reconfigurable Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2014
OCEAN: An Optimized HW/SW Reliability Mitigation Approach for Scratchpad Memories in Real-Time SoCs.
ACM Trans. Embed. Comput. Syst., 2014
ACM Trans. Archit. Code Optim., 2014
Fast and Accurate Architecture Exploration for High Performance and Low Energy VLIW Data-Path.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014
System Level Comparison of 3D Integration Technologies for Future Mobile MPSoC Platform.
IEEE Embed. Syst. Lett., 2014
Worst-case Throughput Analysis for Parametric Rate and Parametric Actor Execution Time Scenario-Aware Dataflow Graphs.
Proceedings of the Proceedings 1st International Workshop on Synthesis of Continuous Parameters, 2014
Degradation analysis of datapath logic subblocks under NBTI aging in FinFET technology.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Understanding timing impact of BTI/RTN with massively threaded atomistic transient simulations.
Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
Energy efficient data flow transformation for Givens Rotation based QR Decomposition.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Energy efficient MIMO processing: A case study of opportunistic run-time approximations.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Adaptive Mapping and Parameter Selection Scheme to Improve Automatic Code Generation for GPUs.
Proceedings of the 12th Annual IEEE/ACM International Symposium on Code Generation and Optimization, 2014
2013
Design Space Exploration of Distributed Loop Buffer Architectures with Incompatible Loop-Nest Organisations in Embedded Systems.
J. Signal Process. Syst., 2013
Survey of Low-Energy Techniques for Instruction Memory Organisations in Embedded Systems.
J. Signal Process. Syst., 2013
Near-optimal and scalable intrasignal in-place optimization for non-overlapping and irregular access schemes.
ACM Trans. Design Autom. Electr. Syst., 2013
System-level memory management based on statistical variability compensation for frame-based applications.
ACM Trans. Embed. Comput. Syst., 2013
Near-Optimal Microprocessor and Accelerators Codesign with Latency and Throughput Constraints.
ACM Trans. Archit. Code Optim., 2013
System scenarios-based architecture level exploration of SDR application using a network-on-chip simulation framework.
Microprocess. Microsystems, 2013
Impact of duty factor, stress stimuli, gate and drive strength on gate delay degradation with an atomistic trap-based BTI model.
Microprocess. Microsystems, 2013
Enabling Efficient System Configurations for Dynamic Wireless Applications Using System Scenarios.
Int. J. Wirel. Inf. Networks, 2013
Design exploration of a NVM based hybrid instruction memory organization for embedded platforms.
Des. Autom. Embed. Syst., 2013
Exploration of energy efficient memory organisations for dynamic multimedia applications using system scenarios.
Des. Autom. Embed. Syst., 2013
ACM Comput. Surv., 2013
Energy impact in the design space exploration of loop buffer schemes in embedded systems.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013
Impact of partial resistive defects and Bias Temperature Instability on SRAM decoder reliablity.
Proceedings of the 8th International Design and Test Symposium, 2013
Proceedings of the IEEE International Conference on Acoustics, 2013
Proceedings of the 18th IEEE European Test Symposium, 2013
Early exploration for platform architecture instantiation with multi-mode application partitioning.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
Sensors, 2012
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012
A template-based methodology for efficient microprocessor and FPGA accelerator co-design.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
Proceedings of the NORCHIP 2012, Copenhagen, Denmark, November 12-13, 2012, 2012
IMOSIM: Exploration tool for Instruction Memory Organisations based on accurate cycle-level energy modelling.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
Impact of Duty Factor, Stress Stimuli, and Gate Drive Strength on Gate Delay Degradation with an Atomistic Trap-Based BTI Model.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Partitioning and Assignment Exploration for Multiple Modes of IEEE 802.11n Modem on Heterogeneous MPSoC Platforms.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Incorporating parameter variations in BTI impact on nano-scale logical gates analysis.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012
Ultra low power litho friendly local assist circuitry for variability resilient 8T SRAM.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
A hybrid HW-SW approach for intermittent error mitigation in streaming-based embedded systems.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the ARCS 2012 Workshops, 28. Februar - 2. März 2012, München, Germany, 2012
2011
J. Signal Process. Syst., 2011
Exploration of Soft-Output MIMO Detector Implementations on Massive Parallel Processors.
J. Signal Process. Syst., 2011
IEEE Trans. Fuzzy Syst., 2011
ACM Trans. Embed. Comput. Syst., 2011
Methodology for Energy-Flexibility Space Exploration and Mapping of Multimedia Applications to Single-Processor Platform Styles.
IEEE Trans. Circuits Syst. Video Technol., 2011
A 4.4 pJ/Access 80 MHz, 128 kbit Variability Resilient SRAM With Multi-Sized Sense Amplifier Redundancy.
IEEE J. Solid State Circuits, 2011
A Lightweight Security Scheme for Wireless Body Area Networks: Design, Energy Evaluation and Proposed Microprocessor Design.
J. Medical Syst., 2011
Systematic Design Principles for Cost-Effective Hard Constraint Management in Dynamic Nonlinear Systems.
Int. J. Adapt. Resilient Auton. Syst., 2011
Run-time self-tuning banked loop buffer architecture for power optimization of dynamic workload applications.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011
Enabling efficient system configurations for dynamic wireless baseband engines using system scenarios.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011
High level analysis of trade-offs across different partitioning schemes for wireless applications.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011
Proceedings of the International SoC Design Conference, 2011
Proceedings of IEEE International Conference on Communications, 2011
Scalable Block-Based Parallel Lattice Reduction Algorithm for an SDR Baseband Processor.
Proceedings of IEEE International Conference on Communications, 2011
8T SRAM with Mimicked Negative Bit-lines and Charge Limited Sequential sense amplifier for wireless sensor nodes.
Proceedings of the 37th European Solid-State Circuits Conference, 2011
An Energy Aware Design Space Exploration for VLIW AGU Model with Fine Grained Power Gating.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
2010
J. Signal Process. Syst., 2010
J. Signal Process. Syst., 2010
IEEE Trans. Veh. Technol., 2010
Implementation of Fuzzy Cognitive Maps Based on Fuzzy Neural Network and Application in Prediction of Time Series.
IEEE Trans. Fuzzy Syst., 2010
Modeling and exploiting spatial locality trade-offs in wavelet-based applications under varying resource requirements.
ACM Trans. Embed. Comput. Syst., 2010
IEEE Signal Process. Mag., 2010
Design of fuzzy cognitive maps using neural networks for predicting chaotic time series.
Neural Networks, 2010
Software metadata: Systematic characterization of the memory behaviour of dynamic applications.
J. Syst. Softw., 2010
Reliability-Aware Proactive Energy Management in Hard Real-Time Systems: A Motivational Case Study.
Int. J. Adapt. Resilient Auton. Syst., 2010
J. Electron. Test., 2010
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010
Proceedings of the International Workshop on Innovative Architecture for Future Generation High Performance Processors and Systems, 2010
Proceedings of the 16th IEEE International Conference on Parallel and Distributed Systems, 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Proceedings of the 18th European Signal Processing Conference, 2010
A 4.4pJ/access 80MHz, 2K word } 64b memory with write masking feature and variability resilient multi-sized sense amplifier redundancy for wireless sensor nodes applications.
Proceedings of the 36th European Solid-State Circuits Conference, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
Proceedings of the 47th Design Automation Conference, 2010
A framework for automatic parallelization, static and dynamic memory optimization in MPSoC platforms.
Proceedings of the 47th Design Automation Conference, 2010
Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010
2009
J. Signal Process. Syst., 2009
Energy Aware Algorithm and Implementation of SDR Oriented HSDPA Chip Level Equalizer.
J. Signal Process. Syst., 2009
Exploiting Varying Resource Requirements in Wavelet-based Applications in Dynamic Execution Environments.
J. Signal Process. Syst., 2009
Design and Synthesis of Pareto Buffers Offering Large Range Runtime Energy/Delay Tradeoffs Via Combined Buffer Size and Supply Voltage Tuning.
IEEE Trans. Very Large Scale Integr. Syst., 2009
Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2009
Generic Multiphase Software Pipelined Partial FFT on Instruction Level Parallel Architectures.
IEEE Trans. Signal Process., 2009
ACM Trans. Design Autom. Electr. Syst., 2009
ACM Trans. Design Autom. Electr. Syst., 2009
Spatial locality exploitation for runtime reordering of JPEG2000 wavelet data layouts.
ACM Trans. Design Autom. Electr. Syst., 2009
IEEE Trans. Circuits Syst. Video Technol., 2009
IEEE Trans. Circuits Syst. Video Technol., 2009
IEEE Trans. Computers, 2009
Microprocess. Microsystems, 2009
A 3.6 pJ/Access 480 MHz, 128 kb On-Chip SRAM With 850 MHz Boost Mode in 90 nm CMOS With Tunable Sense Amplifiers.
IEEE J. Solid State Circuits, 2009
Optimization methodology of dynamic data structures based on genetic algorithms for multimedia embedded systems.
J. Syst. Softw., 2009
Direct memory access usage optimization in network applications for reduced memory latency and energy consumption.
J. Embed. Comput., 2009
J. Commun., 2009
Dealing with data dependent conditions to enable general global source code transformations.
Int. J. Embed. Syst., 2009
Reconfigurable AGU: An Address Generation Unit Based on Address Calculation Pattern for Low Energy and High Performance Embedded Processors.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Des. Autom. Embed. Syst., 2009
Register file exploration for a multi-standard wireless forward error correction ASIP.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009
Power-aware evaluation flowfor digital decimation filter architectures for high-speed ADCS.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009
Proceedings of the Embedded Computer Systems: Architectures, 2009
Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009
Multi-granularity NoC Simulation Framework for Early Phase Exploration of SDR Hardware Platforms.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
Proceedings of the Parallel Computing: From Multicores and GPU's to Petascale, 2009
Proceedings of IEEE International Conference on Communications, 2009
A System Level Algorithmic Approach toward Energy-Aware SDR Baseband Implementations.
Proceedings of IEEE International Conference on Communications, 2009
Proceedings of the IEEE International Conference on Acoustics, 2009
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
Simulation framework for early phase exploration of SDR platforms: A case study of platform dimensioning.
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Algorithm-architecture co-design of soft-output ML MIMO detector for parallel application specific instruction set processors.
Proceedings of the Design, Automation and Test in Europe, 2009
System-level power/performance evaluation of 3D stacked DRAMs for mobile applications.
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009
Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
System-level process variability compensation on memory organizations: on the scalability of multi-mode memories.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
Synthesis of Runtime Switchable Pareto Buffers Offering Full Range Fine Grained Energy/Delay Trade-Offs.
J. Signal Process. Syst., 2008
J. Signal Process. Syst., 2008
Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications.
J. Signal Process. Syst., 2008
Storage Estimation and Design Space Exploration Methodologies for the Memory Management of Signal Processing Applications.
J. Signal Process. Syst., 2008
MEERA: Cross-Layer Methodology for Energy Efficient Resource Allocation in Wireless Networks.
IEEE Trans. Wirel. Commun., 2008
IEEE Trans. Wirel. Commun., 2008
ACM Trans. Design Autom. Electr. Syst., 2008
ACM Trans. Design Autom. Electr. Syst., 2008
Concepts and Implementation of Spatial Division Multiplexing for Guaranteed Throughput in Networks-on-Chip.
IEEE Trans. Computers, 2008
Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures.
Integr., 2008
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
Energy-Efficient Bandwidth Allocation for Multiuser Scalable Video Streaming over WLAN.
EURASIP J. Wirel. Commun. Netw., 2008
Performance Analysis of Slotted Carrier Sense IEEE 802.15.4 Acknowledged Uplink Transmissions.
Proceedings of the WCNC 2008, IEEE Wireless Communications & Networking Conference, March 31 2008, 2008
Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008
A unified instruction set programmable architecture for multi-standard advanced forward error correction.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008
An implementation friendly low complexity multiplierless LLR generator for soft MIMO sphere decoders.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008
Proceedings of the Image Processing: Algorithms and Systems VI, 2008
Selective Spanning with Fast Enumeration: A Near Maximum-Likelihood MIMO Detector Designed for Parallel Programmable Baseband Architectures.
Proceedings of IEEE International Conference on Communications, 2008
Proceedings of IEEE International Conference on Communications, 2008
Spatial locality trade-offs of wavelet-based applications in dynamic execution environments.
Proceedings of the IEEE International Conference on Acoustics, 2008
Bridging the energy gap in size, weight and power constrained software defined radio: Agile baseband processing as a key enabler.
Proceedings of the IEEE International Conference on Acoustics, 2008
Proceedings of the High Performance Embedded Architectures and Compilers, 2008
A tool flow for predicting system level timing failures due to interconnect reliability degradation.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
Proceedings of the Global Communications Conference, 2008. GLOBECOM 2008, New Orleans, LA, USA, 30 November, 2008
Adaptive SSFE Near-ML MIMO Detector with Dynamic Search Range and 80-103Mbps Flexible Implementation.
Proceedings of the Global Communications Conference, 2008. GLOBECOM 2008, New Orleans, LA, USA, 30 November, 2008
A 3.6pJ/access 480MHz, 128Kbit on-Chip SRAM with 850MHz boost mode in 90nm CMOS with tunable sense amplifiers to cope with variability.
Proceedings of the ESSCIRC 2008, 2008
How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous Design.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
Scenario-Based Fixed-point Data Format Refinement to Enable Energy-scalable Software Defined Radios.
Proceedings of the Design, Automation and Test in Europe, 2008
Generic Multi-Phase Software-Pipelined Partial-FFT on Instruction-Level-Parallel Architectures and SDR Baseband Applications.
Proceedings of the Design, Automation and Test in Europe, 2008
Optimizing Near-ML MIMO Detector for SDR Baseband on Parallel Programmable Architectures.
Proceedings of the Design, Automation and Test in Europe, 2008
How to let instruction set processor beat ASIC for low power wireless baseband implementation: a system level approach.
Proceedings of the 45th Design Automation Conference, 2008
Accumulative Interference Modeling for Cognitive Radios with Distributed Channel Access.
Proceedings of the 3rd International ICST Conference on Cognitive Radio Oriented Wireless Networks and Communications, 2008
Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata information.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008
2007
Energy/Area/Delay Tradeoffs in the Physical Design of On-Chip Segmented Bus Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2007
ACM Trans. Design Autom. Electr. Syst., 2007
Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors.
ACM Trans. Design Autom. Electr. Syst., 2007
Incremental hierarchical memory size estimation for steering of loop transformations.
ACM Trans. Design Autom. Electr. Syst., 2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
IEEE J. Solid State Circuits, 2007
J. Syst. Archit., 2007
Systematic methodology for exploration of performance - Energy trade-offs in network applications using Dynamic Data Type refinement.
J. Syst. Archit., 2007
Int. J. Embed. Syst., 2007
Design-time application mapping and platform exploration for MP-SoC customised run-time management.
IET Comput. Digit. Tech., 2007
IET Comput. Digit. Tech., 2007
<i>SmartMIMO</i>: An Energy-Aware Adaptive MIMO-OFDM Radio Link Control for Next-Generation Wireless Local Area Networks.
EURASIP J. Wirel. Commun. Netw., 2007
A Wavelet-FFT Based Efficient Sparse OFDMA Demodulator and Its Implementation on VLIW Architecture.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007
Systematic Optimization of Programmable QRD Implementation for Multiple Application Scenarios.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007
Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems, 2007
Optimization of dynamic data structures in multimedia embedded systems using evolutionary computation.
Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems, 2007
Proceedings of the Embedded Computer Systems: Architectures, 2007
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
Proceedings of the IEEE 9th Workshop on Multimedia Signal Processing, 2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the International Symposium on System-on-Chip, 2007
Using a Linear Sectioned Bus And a Communication Processor to Reduce Energy Costs in Synchronous On-Chip Communication.
Proceedings of the International Symposium on System-on-Chip, 2007
Architectures and Circuits for Software-Defined Radios: Scaling and Scalability for Low Cost and Low Energy.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Real-Time Stereo Correspondence using a Truncated Separable Laplacian Kernel Approximation on Graphics Hardware.
Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, 2007
Fast Variable Center-Biased Windowing for High-Speed Stereo on Programmable Graphics Hardware.
Proceedings of the International Conference on Image Processing, 2007
Proceedings of the IEEE International Conference on Acoustics, 2007
Proceedings of the IEEE International Conference on Acoustics, 2007
Proceedings of the IEEE International Conference on Acoustics, 2007
The Quality-Energy Scalable OFDMA Modulation for Low Power Transmitter and VLIW Processor Based Implementation.
Proceedings of the Global Communications Conference, 2007
Network-adaptive and energy-efficient multi-user video communication over QOS enabled WLAN.
Proceedings of the 15th European Signal Processing Conference, 2007
Proceedings of the 2007 5th Workshop on Embedded Systems for Real-Time Multimedia, 2007
Proceedings of the 2007 5th Workshop on Embedded Systems for Real-Time Multimedia, 2007
Reducing the reconfiguration overhead: a survey of techniques.
Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007
Very wide register: an asymmetric register file organization for low power embedded processors.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Middleware design optimization of wireless protocols based on the exploitation of dynamic input patterns.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
A Distributed Multichannel MAC Protocol for Cognitive Radio Networks with Primary User Recognition.
Proceedings of the 2nd International ICST Conference on Cognitive Radio Oriented Wireless Networks and Communications, 2007
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
Proceedings of the Architecture of Computing Systems, 2007
2006
Platform independent optimisation of multi-resolution 3D content to enable universal media access.
Vis. Comput., 2006
A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck.
IEEE Trans. Very Large Scale Integr. Syst., 2006
Systematic dynamic memory management design methodology for reduced memory footprint.
ACM Trans. Design Autom. Electr. Syst., 2006
ACM Trans. Design Autom. Electr. Syst., 2006
Eliminating CPU overhead for on-the-fly content adaptation with MPEG-4 wavelet subdivision surfaces.
IEEE Trans. Consumer Electron., 2006
Cross-layer power management in wireless networks and consequences on system-level architecture.
Signal Process., 2006
J. Low Power Electron., 2006
Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems.
Integr., 2006
Reducing memory fragmentation in network applications with dynamic memory allocators optimized for performance.
Comput. Commun., 2006
Reliability Issues in Deep Deep Submicron Technologies: Time-Dependent Variability and its Impact on Embedded System Design.
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006
Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design.
Proceedings of the IFIP VLSI-SoC 2006, 2006
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture.
Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006
Exploit Multiple-Domain Sparseness for HSDPA Chip Level Equalization in SDR: Algorithm and DSP Implementation.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006
SmartMIMO: Energy-Aware Adaptive MIMO-OFDM Radio Link Control for Wireless Local Area Networks.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006
Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006
Statistical Performance Analysis and Estimation of Coarse Grain Parallel Multimedia Processing System.
Proceedings of the 12th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2006), 2006
Streaming-Mode MB-Based Integral Image Techniques for Fast Multi-view Video Illumination Compensation.
Proceedings of the Advances in Multimedia Information Processing, 2006
Software Simultaneous Multi-Threading, a Technique to Exploit Task-Level Parallelism to Improve Instruction- and Data-Level Parallelism.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Proceedings of the Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 2006
On the Combined Impact of Soft and Medium Gate Oxide Breakdown and Process Variability on the Parametric Figures of SRAM components.
Proceedings of the 14th IEEE International Workshop on Memory Technology, 2006
Proceedings of the International Symposium on System-on-Chip, 2006
System-level process variability compensation on memory organizations of dynamic applications: a case study.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Systematic design flow for dynamic data management in visual texture decoder of MPEG-4.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
A configuration memory hierarchy for fast reconfiguration with reduced energy consumption overhead.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Proceedings of the 2006 IEEE International Conference on Multimedia and Expo, 2006
Proceedings of the Global Telecommunications Conference, 2006. GLOBECOM '06, San Francisco, CA, USA, 27 November, 2006
Energy-efficient dynamic memory allocators at the middleware level of embedded systems.
Proceedings of the 6th ACM & IEEE International conference on Embedded software, 2006
Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Automated exploration of pareto-optimal configurations in parameterized dynamic memory allocation for embedded systems.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Scalable performance-energy trade-off exploration of embedded real-time systems on multiprocessor platforms.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Dynamic data type refinement methodology for systematic performance-energy design exploration of network applications.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the 1st International ICST Conference on Cognitive Radio Oriented Wireless Networks and Communications, 2006
Yield prediction for architecture exploration in nanometer technology nodes: : a model and case study for memory organizations.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006
Hierarchical memory size estimation for loop fusion and loop shifting in data-dominated applications.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006
Energy Consumption for Transport of Control Information on a Segmented Software-Controlled Communication Architecture.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006
2005
Methodology for Refinement and Optimisation of Dynamic Memory Management for Embedded Systems in Multimedia Applications.
J. VLSI Signal Process., 2005
Energy Efficient Memory Architecture for High Speed Decoding of Block Turbo-Codes with the Fang-Buda Algorithm.
J. VLSI Signal Process., 2005
Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs.
IEEE Trans. Very Large Scale Integr. Syst., 2005
Cache Conscious Data Layout Organization for Conflict Miss Reduction in Embedded Multimedia Applications.
IEEE Trans. Computers, 2005
IEEE Trans. Computers, 2005
Mapping the MPEG-4 visual texture decoder: a system-level design technique based on heterogeneous platforms.
IEEE Signal Process. Mag., 2005
Energy-aware Dynamic Task Scheduling Applied to a Real-time Multimedia Application on an Xscale Board.
J. Low Power Electron., 2005
J. Embed. Comput., 2005
J. Embed. Comput., 2005
Optimizing Transmission and Shutdown for Energy-Efficient Real-time Packet Scheduling in Clustered Ad Hoc Networks.
EURASIP J. Wirel. Commun. Netw., 2005
IEEE Des. Test Comput., 2005
Reducing Memory Fragmentation with Performance-Optimized Dynamic Memory Allocators in Network Applications.
Proceedings of the Wired/Wireless Internet Communications, Third International Conference, 2005
Proceedings of the Proceeding of the Tenth International Conference on 3D Web Technology, 2005
Proceedings of the 9th International Workshop on Software and Compilers for Embedded Systems, Dallas, Texas, USA, September 29, 2005
Moving Up to the Modeling Level for the Transformation of Data Structures in Embedded Multimedia Applications.
Proceedings of the Embedded Computer Systems: Architectures, 2005
Energy Characterization of Garbage Collectors for Dynamic Applications on Embedded Systems.
Proceedings of the Integrated Circuit and System Design, 2005
Proceedings of the Integrated Circuit and System Design, 2005
Performance Evaluation of Barrier Techniques for Distributed Tracing Garbage Collectors.
Proceedings of the Parallel Computing: Current & Future Issues of High-End Computing, 2005
Pack Transposition: Enhancing Superword Level Parallelism Exploitation.
Proceedings of the Parallel Computing: Current & Future Issues of High-End Computing, 2005
Proceedings of the 2005 International Symposium on System-on-Chip, 2005
Architectural and Physical Design Optimizations for Efficient Intra-tile Communication.
Proceedings of the 2005 International Symposium on System-on-Chip, 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
Proceedings of the INFOCOM 2005. 24th Annual Joint Conference of the IEEE Computer and Communications Societies, 2005
Object-Distribution Analysis: Technique for Parallel Loop Distribution of Object-Oriented Programs.
Proceedings of the 34th International Conference on Parallel Processing Workshops (ICPP 2005 Workshops), 2005
Delay improvement of IEEE 802.11 distributed coordination function using size-based scheduling.
Proceedings of IEEE International Conference on Communications, 2005
Optimizing transmission and shutdown for energy-efficient packet scheduling in sensor networks.
Proceedings of the Wireless Sensor Networks, Second European Workshop, 2005
Operation Shuffling for Low Energy L0 Cluster Generation on Heterogeneous VLIW Processors.
Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005
Data-Access Optimization of Embedded Systems Through Selective Inlining Transformation.
Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005
Combining Data and Instruction Memory Energy Optimizations for Embedded Applications.
Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005
Systematic Analysis of Energy and Delay Impact of Very Deep Submicron Process Variability Effects in Embedded SRAM Modules.
Proceedings of the 2005 Design, 2005
Functional Equivalence Checking for Verification of Algebraic Transformations on Array-Intensive Source Code.
Proceedings of the 2005 Design, 2005
A Hybrid Prefetch Scheduling Heuristic to Minimize at Run-Time the Reconfiguration Overhead of Dynamically Reconfigurable Hardware.
Proceedings of the 2005 Design, 2005
A Memory Hierarchical Layer Assigning and Prefetching Technique to Overcome the Memory Performance/Energy Bottleneck.
Proceedings of the 2005 Design, 2005
Energy Efficiency of the IEEE 802.15.4 Standard in Dense Wireless Microsensor Networks: Modeling and Improvement Perspectives.
Proceedings of the 2005 Design, 2005
Compiler-Based Approach for Exploiting Scratch-Pad in Presence of Irregular Array Access.
Proceedings of the 2005 Design, 2005
From myth to methodology: cross-layer design for energy-efficient wireless communication.
Proceedings of the 42nd Design Automation Conference, 2005
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005
A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005
Proceedings of the Compiler Construction, 14th International Conference, 2005
Proceedings of the Compiler Construction, 14th International Conference, 2005
Hierarchical task scheduler for interleaving subtasks on heterogeneous multiprocessor platforms.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Power Breakdown Analysis for a Heterogeneous NoC Platform Running a Video Application.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005
Proceedings of the Programming Languages and Systems, Third Asian Symposium, 2005
2004
Combined Application of Data Transfer and Storage Optimizing Transformations and Subword Parallelism Exploitation for Power Consumption and Execution Time Reduction in VLIW Multimedia Processors.
J. VLSI Signal Process., 2004
Memory-access-aware data structure transformations for embedded software with dynamic data accesses.
IEEE Trans. Very Large Scale Integr. Syst., 2004
ACM Trans. Design Autom. Electr. Syst., 2004
A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs.
Microprocess. Microsystems, 2004
Formally Specifying Dynamic Data Structures for Embedded Software Design: an Initial Approach.
Proceedings of the First International Workshop on Formal Foundations of Embedded Software and Component-based Software Architectures, 2004
IEEE Des. Test Comput., 2004
Des. Autom. Embed. Syst., 2004
Design of Energy Efficient Wireless Networks Using Dynamic Data Type Refinement Methodology.
Proceedings of the Wired/Wireless Internet Communications, Second International Conference, 2004
Dynamic Mapping and Ordering Tasks of Embedded Real-Time Systems on Multiprocessor Platforms.
Proceedings of the Software and Compilers for Embedded Systems, 8th International Workshop, 2004
An Automated C++ Code and Data Partitioning Framework for Data Management of Data-Intensive Applications.
Proceedings of the Software and Compilers for Embedded Systems, 8th International Workshop, 2004
Power, Performance and Area Exploration for Data Memory Assignment of Multimedia Applications.
Proceedings of the Computer Systems: Architectures, 2004
Proceedings of the 2004 ACM Symposium on Applied Computing (SAC), 2004
Proceedings of the 25th IEEE Real-Time Systems Symposium (RTSS 2004), 2004
Proceedings of the Integrated Circuit and System Design, 2004
Modular Construction and Power Modelling of Dynamic Memory Managers for Embedded Systems.
Proceedings of the Integrated Circuit and System Design, 2004
Fast prototyping and refinement of complex dynamic data types in multimedia applications for consumer embedded devices.
Proceedings of the 2004 IEEE International Conference on Multimedia and Expo, 2004
High-Level Data-Access Analysis for Characterisation of (Sub)task-Level Parallelism in Java.
Proceedings of the 9th International Workshop on High-Level Programming Models and Supportive Environments (HIPS 2004), 2004
Design-Time Data-Access Analysis for Parallel Java Programs with Shared-Memory Communication Model.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004
Data assignment and access scheduling exploration for multi-layer memory architectures.
Proceedings of the 2nd Workshop on Embedded Systems for Real-Time Multimedia, 2004
Low energy data and concurrency management of highly dynamic real-time multi-media systems.
Proceedings of the 2nd Workshop on Embedded Systems for Real-Time Multimedia, 2004
Reducing memory accesses with a system-level design methodology in customized dynamic memory management.
Proceedings of the 2nd Workshop on Embedded Systems for Real-Time Multimedia, 2004
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 Design, 2004
Dynamic Memory Management Design Methodology for Reduced Memory Footprint in Multimedia and Wireless Network Applications.
Proceedings of the 2004 Design, 2004
Proceedings of the 41th Design Automation Conference, 2004
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004
Overcoming the "Memory Wall" by improved system design exploration and a link to process technology options.
Proceedings of the First Conference on Computing Frontiers, 2004
A global bus power optimization methodology for physical design of memory dominated systems by coupling bus segmentation and activity driven block placement.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004
Garbage Collector Refinement for New Dynamic Multimedia Applications on Embedded Systems.
Proceedings of the 8th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-8 2004), 2004
2003
J. VLSI Signal Process., 2003
J. VLSI Signal Process., 2003
J. VLSI Signal Process., 2003
IEEE Trans. Very Large Scale Integr. Syst., 2003
Search space definition and exploration for nonuniform data reuse opportunities in data-dominant applications.
ACM Trans. Design Autom. Electr. Syst., 2003
ACM Trans. Embed. Comput. Syst., 2003
A scalable MPEG-4 wavelet-based visual texture compression system with optimized memory organization.
IEEE Trans. Circuits Syst. Video Technol., 2003
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
An Automatic Verification Technique for Loop and Data Reuse Transformations based on Geometric Modeling of Programs.
J. Univers. Comput. Sci., 2003
Efficient System-Level Functional Verification Methodology for Multimedia Applications.
IEEE Des. Test Comput., 2003
Systematic Application of Data Transfer and Storage Optimizing Code Transformations for Power Consumption and Execution Time Reduction in ACROPOLIS: A Pre-Compiler for Multimedia Applications.
Des. Autom. Embed. Syst., 2003
Global interconnect trade-off for technology over memory modules to application level: case study.
Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003
Proceedings of the Software and Compilers for Embedded Systems, 7th International Workshop, 2003
Proceedings of the Software and Compilers for Embedded Systems, 7th International Workshop, 2003
Power Estimation Approach of Dynamic Data Storage on a Hardware Software Boundary Level.
Proceedings of the Integrated Circuit and System Design, 2003
Proceedings of the Integrated Circuit and System Design, 2003
Proceedings of the 2003 Conference on Languages, 2003
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
Automatic functional verification of memory oriented global source code transformations.
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003
Run-Time Minimization of Reconfiguration Overhead in Dynamically Reconfigurable Systems.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003
Application of Task Concurrency Management on Dynamically Reconfigurable Hardware Platforms.
Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003
Run-Time Scheduling for Multimedia Applications on Dynamically Reconfigurable Systems.
Proceedings of the First Workshop on Embedded Systems for Real-Time Multimedia, 2003
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003
SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms.
Proceedings of the 2003 Design, 2003
Proceedings of the 2003 Design, 2003
Background Data Organisation for the Low-Power Implementation in Real-Time of a Digital Audio Broadcast Receiver on a SIMD Processor.
Proceedings of the 2003 Design, 2003
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003
SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms.
Proceedings of the Embedded Software for SoC, 2003
Proceedings of the Embedded Software for SoC, 2003
2002
IEEE Trans. Very Large Scale Integr. Syst., 2002
A systematic methodology for the application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in realizations of multimedia algorithms on programmable processors.
IEEE Trans. Very Large Scale Integr. Syst., 2002
System-level exploration of association table implementations in telecom network applications.
ACM Trans. Embed. Comput. Syst., 2002
J. Circuits Syst. Comput., 2002
Geometric Model Checking: An Automatic Verification Technique for Loop and Data Reuse Transformations.
Proceedings of the Compiler Optimization Meets Compiler Verification, 2002
Incorporating energy efficient data structures into modular software implementations for internet-based embedded systems.
Proceedings of the Third International Workshop on Software and Performance, 2002
Proceedings of the Verification, 2002
Systematic Address and Control Code Transformations for Performance Optimisation of a MPEG-4 Video Decoder.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
Proceedings of the Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), 2002
Data Transfer and Storage Exploration for Real-Time Implementation of a Digital Audio Broadcast Receiver on a Trimedia Processor.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002
A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002
Proceedings of the 2002 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2002), 2002
Multi-ovjective abstract data type refinement for mapping tables in telecom network applications.
Proceedings of The Workshop on Memory Systems Performance (MSP 2002), 2002
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002
Analyzing energy friendly steady state phases of dynamic application execution in terms of sparse data structures.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002
Proceedings of the Global Telecommunications Conference, 2002
Systematic Power-Performance Trade-Off in MPEG-4 by Means of Selective Function Inlining Steered by Address Optimization Opportunities.
Proceedings of the 2002 Design, 2002
Proceedings of the 2002 Design, 2002
System-level performance optimization of the data queueing memory management in high-speed network processors.
Proceedings of the 39th Design Automation Conference, 2002
Kluwer, ISBN: 978-0-7923-7689-7, 2002
2001
Power and Speed-Efficient Code Transformation of Video Compression Algorithms for RISC Processors.
J. VLSI Signal Process., 2001
A Systematic Approach to Reduce the System Bus Load and Power in Multimedia Algorithms.
VLSI Design, 2001
IEEE Trans. Very Large Scale Integr. Syst., 2001
ACM Trans. Design Autom. Electr. Syst., 2001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
IEEE Des. Test Comput., 2001
Guest Editors' Intoduction: The New World of Large Embedded Memories.
IEEE Des. Test Comput., 2001
IEEE Des. Test Comput., 2001
IEEE Des. Test Comput., 2001
Code Transformations for Data Transfer and Storage Exploration Preprocessing in Multimedia Processors.
IEEE Des. Test Comput., 2001
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001
Systematic speed-power memory data-layout exploration for cache controlled embedded multimedia applications.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001
Proceedings of the 14th International Symposium on Systems Synthesis, 2001
Memory hierarchy layer assignment for data re-use exploitation in multimedia algorithms realized on predefined processor architectures.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
Solving large scale assignment problems in high-level synthesis by approximative quadratic programming.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001
Proceedings of the Euro-Par 2001: Parallel Processing, 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Detection of Partially Simultaneously Alive Signals in Storage Requirement Estimation for Data Intensive Applications.
Proceedings of the 38th Design Automation Conference, 2001
2000
A Specification Refinement Methodology for Power Efficient Partitioning of Data-Dominated Algorithms Within Performance Constraints.
J. VLSI Signal Process., 2000
Formalized three-layer system-level model and reuse methodology for embedded data-dominated applications.
IEEE Trans. Very Large Scale Integr. Syst., 2000
Combining Background Memory Management and Regular Array Co-Partitioning, Illustrated on a Full Motion Estimation Kernel.
Parallel Algorithms Appl., 2000
The Local Wavelet Transform: a memory-efficient, high-speed architecture optimized to a Region-Oriented Zero-Tree coder.
Integr. Comput. Aided Eng., 2000
Transformations of a 3D Image Reconstruction Algorithm for Data Transfer and Storage Optimisation.
Des. Autom. Embed. Syst., 2000
A loop transformation approach for combined parallelization and data transfer and storage optimization.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000
Dynamic Memory Oriented Transformations in the MPEG4 IM1-Player on a Low Power Platform.
Proceedings of the Power-Aware Computer Systems, First International Workshop, 2000
Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000
Proceedings of the 13th International Symposium on System Synthesis, 2000
Proceedings of the 13th International Symposium on System Synthesis, 2000
Systematic cycle budget versus system power trade-off: a new perspective on system exploration of real-time data-dominated applications.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000
Proceedings of the Parallel and Distributed Processing, 2000
Task Concurrency Management Experiment for Power-Efficient Speed-up of Embedded MPEG4 IM1 Player.
Proceedings of the 2000 International Workshop on Parallel Processing, 2000
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
Multi-dimensional Selection Techniques for Minimizing Memory Bandwidth in High-Throughput Embedded Systems.
Proceedings of the High Performance Computing, 2000
Formalized Three-Layer System-Level Reuse Model and Methodology for Embedded Data-Dominated Applications.
Proceedings of the 2000 Design, 2000
Proceedings of the 2000 Design, 2000
How to Solve the Current Memory Access and Data Transfer Bottlenecks: At the Processor Architecture or at the Compiler Level?
Proceedings of the 2000 Design, 2000
Proceedings of the 37th Conference on Design Automation, 2000
Proceedings of the 37th Conference on Design Automation, 2000
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000
Storage requirement estimation for data intensive applications with partially fixed execution ordering.
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000
Proceedings of the 2000 International Conference on Compilers, 2000
Proceedings of the 2000 International Conference on Compilers, 2000
1999
J. VLSI Signal Process., 1999
System-Level Energy-Delay Exploration for Multimedia Applications on Embedded Cores with Hardware Cache.
J. VLSI Signal Process., 1999
Energy-Delay Efficient Data Storage and Transfer Architectures and Methodologies: Current Solutions and Remaining Problems.
J. VLSI Signal Process., 1999
IEEE Trans. Very Large Scale Integr. Syst., 1999
IEEE Trans. Very Large Scale Integr. Syst., 1999
IEEE Trans. Very Large Scale Integr. Syst., 1999
Low Power Memory Storage and Transfer Organization for the MPEG-4 Full Pel Motion Estimation on a Multimedia Processor.
IEEE Trans. Multim., 1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
Strategy for power efficient combined task and data parallelism exploration illustrated on a QSDPCM video codec.
J. Syst. Archit., 1999
Transformations of a 3D Image Reconstruction Algorithm for Data Transfer and Storage Optimization.
Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), 1999
Platform Independent Data Transfer and Storage Exploration Illustrated on Parallel Cavity Detection Algorithm.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999
Proceedings of the 12th International Symposium on System Synthesis, 1999
Energy efficient data transfer and storage organization for a MAP turbo decoder module.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999
A methodology for power efficient partitioning of data-dominated algorithm specifications within performance constraints.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
System-level power optimizing data-flow transformations for multimedia applications realized on programmable multimedia processors.
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
Interaction Between Data Parallel Compilation and Data Transfer and Storage Cost Minimization for Multimedia Applications.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999
Proceedings of the 25th EUROMICRO '99 Conference, 1999
Global Multimedia System Design Exploration Using Accurate Memory Organization Feedback.
Proceedings of the 36th Conference on Design Automation, 1999
1998
System-Level Power Optimization of Video Codecs on Embedded Cores: A Systematic Approach.
J. VLSI Signal Process., 1998
System-Level Data-Flow Transformation Exploration and Power-Area Trade-offs Demonstrated on Video Codecs.
J. VLSI Signal Process., 1998
Formalized methodology for data reuse: exploration for low-power hierarchical memory mappings.
IEEE Trans. Very Large Scale Integr. Syst., 1998
High-level address optimization and synthesis techniques for data-transfer-intensive applications.
IEEE Trans. Very Large Scale Integr. Syst., 1998
Program transformation strategies for memory size and power reduction of pseudoregular multimedia subsystems.
IEEE Trans. Circuits Syst. Video Technol., 1998
IEEE J. Sel. Areas Commun., 1998
Techniques for Reducing the Number of Decisions and Backtracks in Combinational Test Generation.
J. Electron. Test., 1998
Power and speed-efficient code transformation of multimedia algorithms for RISC processors.
Proceedings of the Second IEEE Workshop on Multimedia Signal Processing, 1998
Proposal for Unified System Design Meta Flow in Task-Level and Instruction-Level Design Technology Research for Multi-Media Applications.
Proceedings of the 11th International Symposium on System Synthesis, 1998
Power exploration for dynamic data types through virtual memory management refinement.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998
Proceedings of the 12th International Parallel Processing Symposium / 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP '98), March 30, 1998
Code Transformations for Reduced Data Transfer and Storage in Low Power Realisations of MPEG-4 Full-Pel Motion Estimation.
Proceedings of the 1998 IEEE International Conference on Image Processing, 1998
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998
Proceedings of the Euro-Par '98 Parallel Processing, 1998
Energy-Delay Efficient Data Storage and Transfer Architectures: Circuit Technology versus Design Methodology Solutions.
Proceedings of the 1998 Design, 1998
Efficient System Exploration and Synthesis of Applications with Dynamic Data Storage and Intensive Data Transfer.
Proceedings of the 35th Conference on Design Automation, 1998
1997
Practical solutions for counting scalars and dependences in ATOMIUM-a memory management system for multidimensional signal processing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997
Memory Size Reduction Through Storage Order Optimization for Embedded Parallel Multimedia Applications.
Parallel Comput., 1997
Proceedings of the 10th International Symposium on System Synthesis, 1997
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997
Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997
Architectural exploration and optimization for counter based hardware address generation.
Proceedings of the European Design and Test Conference, 1997
Proceedings of the Fifth International Workshop on Hardware/Software Codesign, 1997
Proceedings of the 1997 International Conference on Application-Specific Systems, 1997
1996
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
Proceedings of the 9th International Symposium on System Synthesis, 1996
Proceedings of the 9th International Symposium on System Synthesis, 1996
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996
Reduction of the memory requirements for the VLSI implementation of the 2D-inverse fast wavelet transform, using a space-filling curve.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996
System-level data-flow transformations for power reduction in image and video processing.
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996
Proceedings of the Euro-Par '96 Parallel Processing, 1996
Proceedings of the Euro-Par '96 Parallel Processing, 1996
A Specification Invariant Technique for Regularity Improvement between Flow-Graph Clusters.
Proceedings of the 1996 European Design and Test Conference, 1996
1995
Formalisation of multi-precision arithmetic for high-level synthesis of DSP architectures.
J. VLSI Signal Process., 1995
Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures.
J. VLSI Signal Process., 1995
IEEE Trans. Very Large Scale Integr. Syst., 1995
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995
Mapping real-time motion estimation type algorithms to memory efficient, programmable multi-processor architectures.
Microprocess. Microprogramming, 1995
Parallel programmable architectures and compilation for multi-dimensional processing.
Microprocess. Microprogramming, 1995
J. Electron. Test., 1995
Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995
Background memory management for dynamic data structure intensive processing systems.
Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995
1994
Cellular automata based deterministic self-test strategies for programmable data paths.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994
Parallel Process. Lett., 1994
J. Electron. Test., 1994
Proceedings of the 7th International Symposium on High Level Synthesis, 1994
Is it Possible to achieve a Teraflop/s on a chip? From High Performance Algorithms to Architectures.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
An optimisation methodology for array mapping of affine recurrence equations in video and image processing.
Proceedings of the International Conference on Application Specific Array Processors, 1994
Loop transformation methodology for fixed-rate video, image and telecom processing applications.
Proceedings of the International Conference on Application Specific Array Processors, 1994
1993
An application-specific architecture for the RBN-coder with efficient memory organization.
J. VLSI Signal Process., 1993
IEEE Trans. Very Large Scale Integr. Syst., 1993
IEEE Des. Test Comput., 1993
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993
1992
J. VLSI Signal Process., 1992
Optimized synthesis of asynchronous control circuits from graph-theoretic specifications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992
Proceedings of the Proceedings IEEE International Test Conference 1992, 1992
Proceedings of the Second Great Lakes Symposium on VLSI, 1992
Time Constrained Allocation and Assignment Techniques for High Throughput Signal Processing.
Proceedings of the 29th Design Automation Conference, 1992
1991
J. VLSI Signal Process., 1991
J. VLSI Signal Process., 1991
Partitioning-Based Allocation of Dedicated Data-Paths in the Architectural Synthesis for High Throughput Applications.
Proceedings of the VLSI 91, 1991
Proceedings of the 1991 International Conference on Acoustics, 1991
Automated test pattern generation for the Cathedral-II/2nd architectural synthesis environment.
Proceedings of the conference on European design automation, 1991
Affine transformations for multi-dimensional signal processing on ASIC regular arrays.
Proceedings of the conference on European design automation, 1991
Cathedral-III: Architecture-Driven High-level Synthesis for High Throughput DSP Applications.
Proceedings of the 28th Design Automation Conference, 1991
Signal analysis and signal transformations for ASIC regular array architecture synthesis.
Proceedings of the Algorithms and Parallel VLSI Architectures II, 1991
Array design methodologies for real-time signal processing in the CATHEDRAL-IV synthesis environment.
Proceedings of the Algorithms and Parallel VLSI Architectures II, 1991
Proceedings of the Application Specific Array Processors, 1991
1990
J. VLSI Signal Process., 1990
J. VLSI Signal Process., 1990
Application-specific architectural methodologies for high-throughput digital signal and image processing.
IEEE Trans. Acoust. Speech Signal Process., 1990
Proc. IEEE, 1990
Testability strategy and test pattern generation for register files and customized memories.
Microprocess. Microsystems, 1990
Efficient VLSI Architectures for a High-Performance Digital Image Communication System.
IEEE J. Sel. Areas Commun., 1990
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990
Proceedings of the 10th IAPR International Conference on Pattern Recognition, 1990
Proceedings of the European Design Automation Conference, 1990
Proceedings of the Application Specific Array Processors, 1990
1989
Definition and assignment of complex data-paths suited for high throughput applications.
Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989
1988
Architectural strategies for an application-specific synchronous multiprocessor environment.
IEEE Trans. Acoust. Speech Signal Process., 1988
SAMURAI: A general and efficient simulated-annealing schedule with fully adaptive annealing parameters.
Integr., 1988
Proceedings of the IEEE International Conference on Acoustics, 1988
Proceedings of the IEEE International Conference on Acoustics, 1988