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Abolfazl Roshanpanah

Orcid: 0000-0002-2335-8051

According to our database1, Abolfazl Roshanpanah authored at least 2 papers between 2024 and 2025.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2025
Design and Implementation of a 16-bit Multi-mode 4-Channel Time-Interleaved Delta-Sigma Modulator with SNDR > 106 dB and DCE Compensation Based on FPGA.
[BibTeX]
[DOI]
Abolfazl Roshanpanah
,
Pooya Torkzadeh
,
Khosrow Hajsadeghi
,
Massoud Dousti
Circuits Syst. Signal Process., April, 2025

2024
A Novel Design of 16-bit Multi-Mode 4-Channel Time-Interleaved Delta-Sigma Digital-to-Analog Converter.
[BibTeX]
[DOI]
Abolfazl Roshanpanah
,
Pooya Torkzadeh
,
Khosrow Hajsadeghi
,
Massoud Dousti
J. Circuits Syst. Comput., September, 2024


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