Asier Matallana

According to our database, Asier Matallana authored at least 3 papers between 2016 and 2025.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2025

Fault Tolerant CCS-MPC for Asymmetrical DTP-PMSM Drives Assisted by Fault Detection Algorithm.

Adriano Navarro-Temoche, Josu Jugo, Edorta Ibarra, Iñigo Kortabarria, Asier Matallana

IEEE Access, 2025

2017

Analysis of impedance and current distributions in parallel IGBT design.

Asier Matallana, Jon Andreu, Jose Ignacio Garate, Iñigo Martínez de Alegría, Iñigo Kortabarria

Proceedings of the 26th IEEE International Symposium on Industrial Electronics, 2017

2016

Analysis and modelling of IGBTs parallelization fundamentals.

Asier Matallana, Jon Andreu, Jose Ignacio Garate, Iker Aretxabaleta, Estefania Planas

Proceedings of the IECON 2016, 2016