Atsushi Ohba

According to our database, Atsushi Ohba authored at least 4 papers between 1988 and 1993.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1993

A 5.8-ns 256-Kb BiCMOS TTL SRAM with T-Shaped bit line architecture.

Toru Shiomi, Tomohisa Wada, Shigeki Ohbayashi, Atsushi Ohba, Hiroki Honda, Yoshiyuki Ishigaki, Shiro Hine, Kenji Anami, Kimio Suzuki, Tadashi Sumi

IEEE J. Solid State Circuits, December, 1993

1991

A 7 ns 1 Mb BiCMOS ECL SRAM with shift redundancy.

Atsushi Ohba, Shigeki Ohbayashi, Toru Shiomi, Satoshi Takano, Kenji Anami, Hiroki Honda, Yoshiyuki Ishigaki, Masahiro Hatanaka, Shigeo Nagao, Shimpei Kayano

IEEE J. Solid State Circuits, April, 1991

1989

A 209 K-transistor ECL gate array with RAM.

Hisayasu Sato, Takashi Nishimura, Makoto Tatsuki, Atsushi Ohba, Shiro Hine, Yoichi Kuramitsu

IEEE J. Solid State Circuits, October, 1989

1988

A macro analysis of soft errors in static RAMs.

Yasunobu Nakase, Kenji Anami, Tohru Shiomi, Atsushi Ohba, Shinpei Kayano

IEEE J. Solid State Circuits, April, 1988